Preparation and Characterization of CdO/In6Se7 Thin Film Transistors

In this study, the design and characterization of CdO/InSe thin film transistors (TFT) that are grown onto Au substrates are investigated. The devices are also subjected to a vacuum annealing process at 300 oC to enhance the structure and electrical performance. It was observed that the growth of polycrystalline monoclinic In6Se7 phase of InSe is preferred at this annealing temperature when coated onto Au/CdO substrates. Electrically, noisy negative capacitance effect accompanied with resonance-antiresonance phenomena is observed in the capacitance spectra of the as prepared TFT devices. The annealing of the TFT devices reduced the noise in the capacitance, conductance, impedance, and reflection coefficient and return loss spectral responses. The heat treated TFT devices displayed low bandpass, high bandpass and bandstop filter characteristics in the studied frequency domain (0.01-1.80 GHz) indicating the applicability of these devices as radio wave-microwave resonators.


Introduction
Cadmium oxide substrates are promising layers which find many optoelectronic applications. The CdO substrates are employed for the third and triplet photon generation 1

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Recently, dielectric-loaded waveguides is designed onto CdO transparent substrates for this purpose. These waveguides are nominated as platforms for integrated triplet photon generation which can be used for on-chip wavelength conversion, MIR up-conversion photodetection, and quantum signal processing 1 . CdO substrates are also used for gas sensing 2 . A sensitivity of 20-33% to oxygen gas in the temperature range of 32-200 o C is reported. In addition, CdO substrates are regarded as good layers for the production of photodiodes which can perform well in the visible range of light 3 .
On the other hand, indium selenide thin films coated onto various dielectric substrates are reported to be beneficial for the production of thin film transistors which can handle multiissue at a time 4,5 . As thin film transistors InSe processes high gain and short response time which make it attractive for the fabrication of photodetectors and micro-light emitting diode displays 5 . In 2 Se 3 is also used in the fabrication of nonvolatile memory devices 6 . α-In 2 Se 3 /WSe 2 vertical heterojunction devices are mentioned exhibiting switchable diode characteristics and nonvolatile memory phenomenon. The photodiodes displayed a high on/off ratio at small switching voltages.
The features of the CdO substrates and the wide range of applications of InSe motivated us to bring these two materials together to form a heterojunction device. As the work function (qf) of CdO being 3.45 eV 6 is less than the work function of Au (5.34 eV), the Au/p-CdO form an ohmic interface. Similarly the ohmic contact to n-InSe layer is achieved by 2 54 eV f = ) pads. The Au/CdO/InSe/ Yb thin film transistor (TFT) devices is tested as passive mode device responsive to ac signals. Particularly, here in this work, the TFT devices is structurally, morphologically and electrically evaluated by means of X-ray diffraction, scanning electron microscopy and impedance spectroscopy techniques. An annealing process is also performed to enhance the electrical performance of the TFT transistors.

Experimental Details
Au, Yb, CdO and InSe thin films are prepared by the thermal evaporation technique under vacuum pressure of 10 -5 mbar. The respective source materials were high purity gold wire (99.97%), ytterbium lumps (99.99%), CdO powders (99.99%) and a -In 2 Se 3 (99.99%) poly-crystals. The first Au layer (1.0 m m thick) was coated onto ultrasonically and chemically cleaned glass substrates. The resulting Au metal films were used as substrate to grow CdO films (0.5 m m thick). The Au/CdO films were coated with InSe layer of thickness of 0.5 m m. The resulting Au/CdO/InSe films are masked and coated with pad shaped Yb films. The area of each pad was . The geometrical design of the device is shown in the inset of Figure 1. The films thicknesses were monitored with Inficon STM-2 thickness monitor attached to the system. The produced Au/CdO/InSe/Yb films were heat treated at 300 o C for one hour under vacuum pressure of 10 -5 mbar. The heating rate before reaching the targeted temperature was ~20 o C/min. The X-ray diffraction was recorded with the help of Miniflex-600 X-ray diffraction unit at scanning speed of 0.1 o /min. The surface morphology was scanned using COXEM 200 SEM system. The impedance *e-mail: atef.qasrawi@atilim.edu.tr spectroscopy was collected between Au (base) and top Yb contact using Agilent 4291B 0.01-1.80 GHz impedance analyzer. The connections to the 16453A dielectric material test fixture were made by AP-7 connector attached to the analyzer.

Results and Discussion
The X-ray diffraction patterns for the Au, as prepared Au/CdO/InSe (ACI) and annealed Au/CdO/InSe thin films are shown in Figure 1. The heterojunction ACI devices were annealed at 300 o C for one hour in a vacuum media of 10 -5 mbar. It is clear from the figure that the as prepared heterojunction devices exhibit amorphous nature of growth owing to the appearance of no extra peaks other than that of gold substrate. The analysis of the peaks which are reflected from the gold thin film substrates indicated the existence of the face centered cubic structure with best plane orientation along the (111) direction. The lattice parameters of the as prepared Au unit cell is found to be . The reflection peaks of the Au substrates also included one peak that is assigned to orthorhombic Au 2 O 3 ( =12.827 Å,=10.520 Å, =4.038 Å 7 ). On the other hand, as displayed in Figure 1, annealing the samples at 300 o C, induced the crystallization process in the ACI heterojunction devices. Namely, new peaks other than that of gold appear in the XRD patterns. Our theoretical investigations on the polycrystalline phases of InSe and CdO using "Crystdiff" software packages have shown that none of these peaks can be assigned to the cubic CdO ( . a 4 696 Å = ) 8 . Excluding the Au peaks as they already exist in the XRD patterns, none of the peaks can also be assigned to the hexagonal CdO which is mentioned displaying peaks at 33.31 ○ (111), 38.40 ○ (200) and 55.65 ○ (220) 9 . Trails to index the experimental data of the annealed ACI sample assuming the growth of hexagonal ( ) , , a b g -In 2 Se 3 10,11 , orthorhombic In 4 Se 3 11 and monoclinic In 6 Se 7 has shown that all the experimentally observed peaks can be assigned to the monoclinic In 6 Se 7 phase of indium selenide 12 . The lattice parameters of the obtained monoclinic unit cell are found to be .
. o a 9 433 b 4 064 c 17 663 and 100 92 The lattice paropameters are consistent with literature data 12 and the crystallography open database (COD NO: 8104059). The unit cell of this structural phase is demonstrated with the help of "Crystalmaker" software packages in Figure 2a. As illustrated, the unit cell is composed of two separate sections of cubic close-packed arrays of selenium atoms with indium atoms in octahedral coordination. The two parts of the cell are located across the center and end sections of the unit cell and may be brought into the same orientation direction through rotating one of them by 61 ° about the [010] direction. The calculated bond lengths with the help of the "crystalmaker" software packages vary in the range of 2.66 Å (In4-Se2) to 2.76 Å (In1-In2). Figure 2b and c show the surface morphology of the as prepared and annealed Au/CdO/InSe heterojunction devices, respectively. While the enlargement of 20,000 times displays randomly distributed circularly shaped grains of average sizes of ~150 nm, the same enlargement of the annealed samples display mostly randomly distributed rectangular grains of sizes of 120 nm. The density of grains on the surface is higher for the as prepared thin film transistors than those which were annealed at 300 o C for one hour. It is mentioned that the size of recrystallized grain is identified by both the nucleation and growth rates. For non-oriented electrical steels, it was found that during the annealing process, if the heating process is fast, less recovery take place 13 . This leads to the storage of extra energy in the crystallites before the recrystallization is initiated. Higher stored energy increases the nucleation rate faster than the growth rate. For this reason, the annealing by fast heating forces the formation of smaller grain sizes than that of slow heating 12 . Other studies accounted the decrease in the grain size upon annealing to the quantum size effect (QSE) 14 . It was shown that the growth dynamics and morphology of grains (islands on thin films) can be well controlled through the quantum size effects defined by Figure 1. the X-ray diffraction patterns for Au, as prepared Au/CdO/InSe and for the annealed Au/CdO/InSe thin film transistors. The inset shows the geometrical design of the device. the island thicknesses and the interplay with the classical forces 15 . The QSEs are mentioned predominating both the formation and stability of thin films at nanoscale levels.
On the other hand, free energy costs from steps provide the usual "classical" driving force to smoothen the film's surface. The restrictions of growth of grains along particular plane direction, forces quantization of this direction, as a result the only possible energy stabilization which is gained by annealing is achieved via grain growth along the remaining two directions. Figure 3a and b show the heat treatment effects on the capacitance (C ) and conductance (G) spectra for the Au/CdO/InSe/Yb devices. It is clear from the Figure 3a that the capacitance of the as prepared Au/CdO/InSe/Yb thin film transistors exhibit resonance peaks at three different critical frequency values. Namely, one may observe strong resonance peaks at 0.15 GHz followed by antiresonance peak at 0.16 GHz. The second resonance peak appears at critical frequency value of 0.40 GHz. The third antiresonance peak is centered at 1.44 GHz. Annealing the devices at 300 o C for one hour leads to the disappearance of these peaks and force the capacitance spectra to exhibit one antiresonance peak centered at 1.10 GHz. While the capacitance spectra of the as prepared ACI devices fluctuates exhibiting positive  and negative values, the capacitance spectra of the annealed devices remain positive for all signal frequencies less than 1.10 GHz and negative for all frequency values larger than 1.10 GHz. Negative capacitance effect is ascribed to many reasons like minority carrier injections caused by accumulation of minority carriers at the grain boundaries 16 . The dense and random distribution of the grains in the as prepared samples that appears in Figure 2b could account for the random fluctuations in the capacitance spectra. Namely, the random distribution and different sizes of grains causes narrow and wide energy barriers at the grain boundaries. This leads to potential barriers of different depths and widths. Each of these barriers behaves as charge accumulation layers that differs in character than the other resulting in a random responses of capacitance to ac signals as observed. The crystallization process and the less dense grains that are achieved by the annealing of the devices (Figure 2c) may be regarded as a reason for the enhanced behavior of capacitance spectra. The negative capacitance effect can also be attributed to the carrier capture and emission at the CdO/ InSe interface states. The process of capture and emission through the interface states were previously observed for InN/ GaAs heterojunctions 17 . On the other hand, the existence of resonance-antiresonance peaks in the capacitance spectra of Au/CdO/InSe/Yb TFTs could be assigned to the oscillations of electric dipoles with or against the propagating ac signals 18 . As the signal propagation is limited by the plasmon frequency of the dielectric media, the formation of the heterojunction from two different materials should lead to at least two plasmon frequencies arising from electrons at one side and from holes at the other side. The plasmon frequencies force the dipoles to exhibit resonance when the signal frequency values approaches that of plasmon 18 . Figure 3b illustrates the annealing effects on the conductance spectra of the studied Au/CdO/InSe/Yb devices. It is clear from the figure that the conductance of the as prepared samples exhibits one local and one absolute maxima at 0.25 and 1.49 GHz, respectively. The shape of the G f -variation in the as prepared devices comprises noisy signals. Annealing the devices leads to more stable G f -variation, caused disappearance of the local peak, shifts the maxima to 1.09 GHz and make the peak width broader. The increase in the values of the conductance with increasing signal frequency up to a critical frequency value which is followed by a decrease in the conductance value with increasing frequency is attributed to the presence of more than one conduction mechanism in the devices. These trends of variations of the conductance spectra are assigned to the combined current conduction of tunneling and correlated barriers hopping (CBH) mechanisms 17 . Similar to our observation for ACI samples, the conductivity spectra of CdS/ Sb 2 Te 3 heterojunction devices have shown maximum peak at 0.26 GHz. The behavior of the conductivity was ascribed to the tunneling in the narrow depletion width and to the CBH owing to the hopping of charge carriers between defect centers over the potential barrier 17 . As the crystalline phase of InSe which is achieved by the annealing process exhibit lower surface defect density than the amorphous films, one may expect modifications in the current conduction mechanism which leads to the observed behavior of conductance. Other heterojunction devices which exhibit similar conductance spectra assigned this behavior to the same current conduction mechanisms 19 . Namely, the alternating current transports mechanism in TiO 2 /ITO/ZnO:Al/p-Si structure is assigned the response of a thermally activated traps to the ac signal frequency 19 . The conduction is observed to be governed by the correlated barrier hopping mechanism involving two distinct energy levels at low frequencies. In the high frequency region, conduction is dominated by the overlapping large-polaron tunneling mechanism 19 .
The total effect of resistive, inductive and capacitive parts is better observed from the impedance (Z) spectra which is illustrated in Figure 4a. The impedance spectra of the as prepared TFT devices display a broadened peaks centered at 0.49 GHz. It also shows an increasing trend of variation in the frequency domain of 1.50-1.80 GHz. The annealing of the ACI devices display a different style of variation. Namely, the impedance decreases with increasing frequency in the frequency domain of 0.01-1.05 GHz. It, then, sharply increases with increasing frequency. It increased from 7.8 W at 1.05 GHz to 143.0 W at 1.77 GHz. The frequency based switching in the impedance value from low to high impedance modes is an indication of the band filtering property. These signs are assured by calculating the magnitude of the reflection coefficient ( 20 of the devices before and after annealing. The calculated reflection coefficient spectra are shown in Figure 4b. It represents the quality of the impedance match between the source of the signal and the measured device under study. r is small for good matches. It takes values from −1 for shorts, is zero for perfect matches and reaches +1 for open loads. As the figure shows, the as prepared ACI devices display one local and one absolute minima at signal frequency values of 0.58 and 1.78 GHz, respectively. The . The higher the absolute value of the return loss, the better the match, the more accurate the data transfer. r L is a measure of the power that is not absorbed by the load and is therefore returned to the source. Large absolute values of r L (greater than |20| dB) indicate a good match. The calculated return loss spectra are shown in Figure 4c. It is clear from the figure that while the as prepared heterojunction ACI devices hardly reaches the standard values (~20 dB), the annealing enhances the return loss values significantly in the high pass mode (0.01-0.47 GHz). It also shows acceptable values 21,22 of r L at the notch frequency (1.53 GHz) while operating in the band stop mode (0.89-1.80 GHz).
The novelty of the current study lay in finding a procedure to improve the performance of the proposed band pass/stop filters and microwave cavities that are made of Au/CdO/InSe/ Yb thin films. The annealing of the devices in a vacuum media at high temperature for one hour improved the response to the propagating ac signal in the devices. Noise is remarkably reduced and negative capacitance effect that is needed for parasitic capacitance cancellation become more pronounced. In addition, better matches between the propagating signals and devices is achieved by this procedure.

Conclusions
In the current study, we have shown that the annealing of Au/CdO/InSe/Yb thin film transistors at 300 o C in a vacuum atmosphere (10 -5 mbar) can enhance the performance of the devices significantly. Particularly, the success of the annealing process to transfer the amorphous structure of InSe to the monoclinic polycrystalline phase is accompanied with improvements in the electrical properties. The annealing reduced the signal distortion, enhanced the negative capacitance effect at high frequencies and forced the devices to exhibit band pass/stop features. The annealed devices displayed return loss value that exceeds the standards in the megahertz frequency domain where the device behaves as high band pass filters and, approximately, reaches standards in the Gigahertz frequency domain where the device behaves as band stop filters. The annealing process makes the Au/CdO/InSe/Yb devices more appropriate for use as microwave cavities.