A passive-matched 22 GHz 2.6-dB-NF CMOS front-end with a 70-800 ps delay block

Department of Electrical and Electronic Engineering, Bangladesh University of Engineering and Technology, Dhaka-1000, Bangladesh, Email: [e-mail]

ABSTRACT

This paper presents a power-efficient RF differential receiver front-end supporting transmitted-reference (TR) communication in a 90 nm CMOS technology. Particularly, it addresses the issues of designing the frontend amplifier with low-noise and passive matching circuits on a silicon process and integrating a low-power delay unit in the front-end with wideband characteristics. The proposed architecture includes a differential high simulated gain (11 dB) amplifier which is centered at 21.6 GHz (in the K-Band) with a 6.2 GHz bandwidth (18.1~24.3 GHz). The input and output reflection parameters have centered values around -26 and -18 dB, respectively. With noise matching, the amplifier achieves 2.6~2.9 dB bandwidth noise-figure and 2 dBm input power limit for linear coverage. To interface the amplifier with a following RF mixer, a submicron delay-block (DB) is proposed with provision of adjusting number of stages in the delay chain. The branched DB architecture achieves monotonic delays covering a range of 70-800 ps (including group-dispersion). Tweaking of delay is possible through four design parameters and the set-up is analyzed by extending the number of cascaded stages up to eight. Driven from a 1.2 V supply, the amplifier and the DB consume 13.9 and 8.52- 10.61 mW power, respectively, and realize the circuits for the TR front-end. When compared with simulated results of reported CMOS receivers, the proposed design delivers higher performance in terms of a microwave figure-of-merit.

Index Terms: CMOS Front-End, TR, Differential Amplifier, Delay-Block.

I. INTRODUCTION

In recent literature, on-chip wireless interconnects have been reported as alternatives to traditional metallic inter-chip communication which becomes possible due to scaling down of CMOS integrated circuits [1], [2], [3]. In this regard, ultra-wideband (UWB) transmission has been cited as a standard which could facilitate chip-scale wireless communication for short-distance low-power applications [4]. For intra-chip and inter-chip data transfer at submicron level, parasitic elements contributed by metallic wiring and device junctions are primarily responsible for introducing undesirable temporal dispersion within the system. This phenomenon can restrict the operating frequency of an RF font-end and limit its achievable data rate. Before transistors in a receiver circuit can move up to a spectrum above C-band (5 GHz), they have to adopt a modulation technique which can reduce these parasitic effects. A UWB receiver front-end with an integrated antenna can facilitate this process by moving the transmission system to a wireless domain [5]. The wideband nature of a UWB receiver can also offer additional benefits like provision to include multiple access capability and greater resistance against interference and multipath fading [6], [7], [8]. To avail these opportunities, the Federal Communications Commission has decided to allow UWB transceivers to operate in frequency ranges shared by other networks as low power density of UWB does not create interference in overlapping bands [9]. Still, proposing a satisfactory mathematical model for channel estimation remains a significant design problem for a wideband technique. The transmit-reference (TR) model, which embeds a synchronizing reference pulse within each streaming frame of data, offers a possible solution for this problem by making separate pilot-carriers redundant for receiver synchronization [10].

A typical TR receiver front-end constitutes a wideband amplifier immediately following the antenna and a self-synchronizing delay-block (DB) preceding an RF mixer [11]. As the input interfacing component of this front-end, a ~22 GHz low noise differential amplifier is presented in this paper with a 90 nm CMOS process. Supported by inductive tuning circuits, the amplifier operates between 18.1 and 24.3 GHz in the K-band which can be used for short-distance wireless transmission. The design does not require a separate current source to control its tail current and uses passive matching techniques to circumvent the need for active matching circuits at interfacing ports. The front-end forward gain (S₂₁) is 11 dB at 21.6 GHz and covers a 6.2 GHz simulated 3-dB bandwidth. While being unconditionally stable according to Rollet criterion, the amplifier dissipates ~14 mW power and may use a balun for port interfacing. In the next step, the architecture of a CMOS delay-block is portrayed which is capable of uniformly delaying wideband pulses without using bipolar power rails in the front-end. It uses basic inverter gates but employs a branched architecture to process input UWB pulses for all polarities and implement a wideband delay line necessary in a TR-receiver. Results show that, amount of pulse-delay provided by the delay-block can be regulated between 70 and 800 ps with fine tuning and low group-dispersion. The proposed integrated front-end requires ~23-24 mW power (including amplifier and DB) and suffers from low noise penalty (< 3 dB).

The paper is laid out as follows. Section II explains the architecture of a TR-receiver with emphasis on the proposed integrated front-end components. The circuits of the wideband low-NF differential amplifier and the synchronizing tunable delay-block are discussed in Sections III and IV, respectively. Section V documents the simulated figures of merit of the proposed circuits. Finally, Section VI summarizes the performance of the front-end components and compares them with examples from published literature.

II. ARCHITECTURE OF A TR TRANSCEIVER

In a transmit-reference (TR) system, the feature of self-controlled synchronization is incorporated by embedding a reference pulse in the data frame of a message signal. The reference peak facilitates receiver synchronization when a proper amount of delay is introduced to the received modulated signal pulses. This temporal shifting is realized with a wideband delay-block (DB) which ultimately produces a pseudo-template signal for the mixer in the receiver. A simplified model of a TR transmitter is presented in Fig. 1(a) which includes an UWB pulse generator block (PG) [10]. The reference or synchronizing (sync.) pulses generated by the PG are delivered to an RF combiner before being transferred to a transmitting antenna. The particular shape of the wideband pulses usually resembles that of a monocycle gaussian pulse. The data or message pulses (produced by the same PG) are delayed by the control mechanism of a delay-block (DB) and a radio-frequency mixer modulates them with the message signal. The RF combiner merges these modulated and reference pulses to form a frame for transmission where pulse repetition rate is regulated by the source pulse generator. So, the back-end of the TR transmitter consists of an RF combiner and a correlating RF mixer. In Fig. 1(b), the proposed TR front-end which immediately follows the receiving antenna is highlighted. It produces two responses in the form of a low noise wideband amplifier output and a delayed version of the received stream from a delay-block (generating a pseudo-pilot signal). The RF mixer in the receiver is fed with these excitations and the mixer output is processed by a window decision circuit to recover message bits encoded in the transmitted signal. Ultimately, the CMOS front-end formed with the matched amplifier and the delay-block plays a crucial role in determining noise performance and detection accuracy of a TR-receiver. This paper proposes circuit schemes to implement the proposed front-end's design blocks which will support the realization of a submicron TR-receiver.

 

III. WIDEBAND DIFFERENTIAL FRONT-END

This section focuses on the front-end in a TR-receiver which is initiated with a low noise wideband amplifier with high-gain characteristics. The proposed front-end employs a differential amplifier to avail the benefits of the differential architecture for a transmit-reference receiver circuit. It facilitates the RF mixer which is always present in the receiver to adopt a double-balanced structure (like a Gilbert mixer) and allows the circuit to be differential up to the decision section of its back-end. At the same time, this topology has to satisfy a relatively high power and area requirement. Despite this constraint, optimization of device sizes and bias currents keep the power demand for the proposed amplifier below 15 mW. As the half circuits in the amplifier core and the matching networks are symmetric in nature they make the architecture more flexible against variation of process. Other advantages include common mode noise suppression for substrate, greater reduction of power rail noise, and compatibility with dipole antenna and image rejection techniques. The differential front-end is also able to achieve a wider range of linear behavior by improving the results of the amplifier's second inter-modulation product (IP₂) [12]. The proposed amplifier architecture is presented in Fig. 2 with interfacing balanced-unbalanced (balun) circuits. In this topology made with common-source converted-to-cascode half-circuits, L_d.12 and L_d.22 resonate with the gate-drain parasites of adjoining transistors (T₁₂ and T₂₂, device ratio: 50µ/0.1µ) and tuning capacitors to define the central operating frequency. The bias current through the individual half-circuits is controlled by dimension of driving devices (T₁₁ and T₂₁, aspect ratio: 43µ/0.1µ) and gate biasing voltage (V_gate), resulting in the exclusion of a separate tail current source in series with the half-circuits. Apart from the reactance L_d.12, the resonance tank of insulating transistor T₁₂ constitutes a fine-tuning parallel capacitor (C_r.12) and a small resistor (R_d.12) modeling parasitic resistance contributed by the on-chip inductor. Similarly, C_r.22 and R_d.22 are parts of the tank built on the second isolating transistor T₂₂. These insulating cascode devices introduce high resistance to reverse leakage and ensure isolated port operation for matching. To pre-bias the active input transistors T₁₁ and T₂₁, a bias circuit is formed with the device T_gate (2µ/1 µ) which supplies the dc gate voltage V_gate (= 0.851 V) through a couple of impeding resistors (R_gate1/25 k). In order to match the input impedance presented by the left-half circuit to 50 in Fig. 2, a reactive LC branch (C_in.11 and L_g.11) is appended with the input gate of T₁₁ along with a degenerating source element L_s.11. This branch couples the input driving signal through port RF_in1, reduces the magnitude of imaginary element present in input impedance, and matches the real part of port impedance to antenna resistance over centered bandwidth. C_in.21, L_g.21 and L_s.21 provide a similar service for the input device T₂₁ in the right-half of this amplifier circuit. If g_m.x is a process conductance parameter (for transistor x), C_gs.x represents parasitic elements at the gate terminal of input transistors, and the degenerating inductor L_s.11 is connected with the source of T₁₁, input interface impedance of the amplifier without any matching can be modeled as [13]

After L_s.11 adjusts real element of input impedance and forward gain, equation (1) is modified with the addition of L_g.11 in the input circuit

The final equation for input impedance matching is achieved after the LC branch is expanded with the coupling capacitor C_in.11

Input matching reduces the reactive components and modifies this expression to match it with R_ant which is the antenna resistance preceding the front-end amplifier. A similar expression can be derived for the right-half of the differential amplifier circuit. A balun-block will be necessary at the RF_in.1/2 ports for single to double ended signal conversion at amplifier input ports. Three coils (L_b.4-6) in a transformer formation execute this balanced to unbalanced transformation process with coupling parameters K_45/46.

Among the active devices of the amplifier, T₁₁ and T₂₁ are responsible for a significant share of thermal-noise. To emphasize this point, we may define a noise factor (NF_drive) for noise induced at gate and drain terminals of the driving transistors. The noise components for these devices are its channel noise factor (Niquist factor) , gate terminal noise coefficient , correlation factor between drain and gate noise co_gd, and effective quality factor of the input stage Q_inp. NF_drive also depends on amplifier center frequency (ω_o) and unity-gain transit frequency of transistors (ω_T ) [14]:

where is defined as

with g_m.11 = input device transconductance and g_do.11 = zero-bias drain conductance of T₁₁. Accounting influence of driving source impedance (R_s) and gate-source inductors of input transistor, input quality factor in equation (4) can be defined as

As expression of noise factor for a driving device has components accounting for drain noise, gate noise, and correlation between the two terminals and components containing in this equation have opposing polarities, they are exploited through an optimization process to reduce the noise factor. Noise components for NF_drive also include series resistance contributed by the inductor L_g.11 (R_g.11), gate-resistance of the input device (R_gate.11), and a process factor which is proportional to the square of input quality factor (Q_inp²) [15]. Hence NF_drive can be expressed with another function with the form of

Typical values for these process dependent device parameters can be modeled as σ=0.667, =1.33, =1, and co_gd= .39j for long channel devices and σ =2.5, =5, =1, and co_gd= .4j for short channel devices [16], [17]. After canceling out the undesired elements in equation (4) with the optimization process (which keeps the power dissipation below a fixed limit), expression for minimum noise factor is simplified to two noise components (conductance ratio and channel noise factor ) apart from the operating amplifier frequencies

For limited power dissipation and submicron devices, σ and are replaced by suitable device constants leading to

The existence of parasitic elements at the node between input and cascode devices makes noise contribution of the cascode transistor T₁₂ significant, which adds on the noise factor of the overall amplifier. The sources of cascode noise factor (NF_cascode) in the proposed amplifier are the estimated parasitic capacitance associated with the intermediate node between T₁₁ and T₁₂ (C_param), zero-bias drain conductance of cascode transistor (g_do.12), secondary device transconductance (g_m.12), driving source impedance (R_s), and a bias dependent parameter ( ϒ₁₂) [18] which lead to

where C_param is approximated by

Therefore, an overall noise factor of the left-half section of the amplifier circuit in Fig. 2 can be estimated by NF_drive and NF_cascode and an identical factor will be applicable for T₂₁ and T₂₂ in the right-half amplifier circuit.

For the output matching circuit connected at the amplifier's left load port (RF_out.1), a design equation can be formulated for the matching components as [19]

For the load-port matching circuit in the proposed design, ideally R_load.1 = Z_mixer()= 50 and R_out.11 = Z_out.11() = 113 in K-band (at 21.6 GHz). So, from equation (14)

A similar model equation can be obtained with C_o.22, C_d.22, and L_o.22 for the right-half amplifier circuit as

In this half-circuit R_load.2 = 50 , R_out.21 = Z_out.21() = 112 Ω near 22 GHz and consequently

As expected, the two symmetrical matching half-circuits produce similar output port impedances (at RF_out1/2) for the overall amplifier. Finally, an output balun block supports the interfacing of the amplifier with a following delay-block. To generate a direct feed for a double balanced differential Gilbert mixer, the load ports may also be linked to the mixer RF ports through small impedances. The three coils for simulating the load-port balun are designated as L_b.1-3 which are linked with carefully selected coupling constants K_12/13. In actual practice, additional fine tuning of reactive components are necessary in the amplifier circuit to obtain a sound matched response and optimize gain and noise performance.

IV. THE SYNCHRONIZING DELAY-BLOCK

As shown in Fig. 1(b), a TR-receiver can support self-synchronizing demodulation because it does not need a separate template signal for the RF correlator (mixer) in its front-end. But to realize this feature, it will require a delayed version of the received pulse-train through a wideband delay-block (DB). This delay-block should be able to handle high data rate of reference pulses and regulate them in a controlled manner. Design criteria warrant compatibility of the delay-block with different amplifier topologies as it is placed between a low noise amplifier and a radio-frequency mixer in the receiver chain. Usage of variable delay units have been reported in applications ranging from voltage controlled oscillators (VCO) to pulse width control systems (PWCL) [20]. But a wideband delay-block for a TR-receiver demands special focus on minimizing power dissipation as the system needs to keep the average power density to the lowest permissible level [21]. Moreover, these delay elements require wideband characteristics to be able to handle pulses with a duration of 10^-10 s.

The proposed architecture of a divided wideband delay-block (DB) built with 90 nm transistors and capable of processing bipolar message carrying pulses [22] is presented in Fig. 3. At its input port, the delay-block has an optional three-coil signal conversion block (L_b7, L_b8, and L_b9) to generate separate excitations for its top and bottom branches (at nodes b and c). No loss in strength of the input feed is assumed in the conversion process (ideal coupling). The bottom feed is added with a bias voltage (V_dd=1.2 V) through a resistive summer to generate an elevated pulse train (at node d). To drive the delay-block and verify its delay regulation, an 800 mV test signal is applied to the proposed architecture. The strength of these test pulses can be tuned by adjusting the gain granted by the preceding amplifier. The primary objective of using two parallel sections in the circuit is to ensure uniform delay for all member pulses in the driving stream and power the delay block with a single bias rail (V_rail). For a single-stage DB, as shown in Fig. 3, the sectional delay chains (stage_top.1 and stage_bot.1) are built with a pair of cascaded inverter blocks and two intermediate capacitors. The unit stage_top.1 is formed with devices T_up.1 (14µ/0.1µ), T_up.3 (1µ/0.1µ), T_up.2/4 (16 µ/0.1µ) and drain-source shorted transistors contributing junction capacitance (C_int.1=2, in the range of 100 fF ). The driving stream for the bottom unit (stage_bot.1) has a base voltage offset of 0.6 V and a different peak-to-peak coverage. As a result, it uses transistors with adjusted dimensions {T_bot.1 (20µ/0.1µ), T_bot.3 (8µ/0.1µ), T_bot.2/4 (16 /0.1 )} and 50 fF shunt capacitors (C_int.3/4). Output from these parallel units (at points x and y) produces nearly uniform delays for bipolar pulses (average of 180 ps for a single block). In order to process negative pulses, the driving stream base was elevated to the 0.6 V range at the start of the bottom unit. As a result, a dc component of 1.0 V is present in the delayed signal at node y of stage_bot.1. This element is removed by an RC branch (made of R_f.1 and C_f.1) and the pulse base is brought back to near ground level. R_add.3 and R_add.4 form a second resistive summer which combines the sectional responses to generate a complete delayed pulse train at node z with relatively small signal dispersion. The overall delay achieved by the proposed single-stage DB is not fixated at 180 ps but can be fine tuned with a number of design parameters [22], as will be explained in the following sections.

The branched architecture of the delay-block allows extension of number of stages in each section (up to eight) during the testing process. Fig. 4 presents a four-stage wideband delay-block where eight delay units (stage_top.1-4 and stage_bot.1-4) are divided between two sections/branches of the design. The device sizes (mentioned in the figure) remain consistent for the top section but need to be adjusted to deal with base elevated pulses in the bottom section. The progress of the delayed pulses at the intermediate nodes (m_i and n_j with {i, j}=1-4) is shown in the diagram which indicates a regular and monotonic variation of achieved delay. The four-stage DB introduces an average overall delay of ~420 ps and the difference in temporal positions of the negative pulse (t₂+450 ps at node w and t₂+420 ps at point z) can be attributed to the resistive summation process. By controlling gain provided by the amplifier preceding the delay-block, the strength of input pulses and magnitude of dc offset needed in the bottom section can be predesigned. Since the wideband pulses are essentially regenerated in this scheme, no matching circuit will be needed for the delay-block as in the cases of LNA and RF mixer in the receiver chain. Further discussion on tuning and regulation of the proposed delay-block is documented in the result section.

The expression for propagation delay achieved by the complete delay chain indicates a non-linear relationship between overall delay and number of stages or individual delay units in top and bottom sections. The pair of cascaded inverters in a single-stage branch, as shown in Fig. 3, controls the component delay with rail voltage (V_rail), shunt reactance (C_int), and device dimensions (W/L ratio) working as design parameters. For a single inverter gate, the value of saturation current flowing through the transistors (I_saturation) is considered as average bias tree current and approximated by

where the device (pull-down) threshold level is designated as V_th.n and G_n is transistor transconductance gain. A mirror equation obtained for the pull-up device will produce the same magnitude for the bias current. If strength of input pulses and voltage of bias rail are regulated in the circuit then the following relationship can also be maintained

After we define t_del.high.low and t_del.low.high as propagation delays for the signal during high-to-low or low-to-high transition at inverter output and C_shunt as intermediate shunt capacitance, unit inverter-delay for a delay gate can be derived as [23]

If R_eq.p and R_eq.n represent equivalent resistances when pull-up and pull-down transistors are 'on', FET signal transition times will be proportional to time constant of RC networks formed by device (which is on) resistance and shunt (load) capacitors. When signal drops from high to low at inverter output, the reactive network is realized with R_eq.n and output capacitance C_shunt. On the other hand, R_eq.p becomes part of this RC circuit in case of low to high transition at gate output. Therefore, propagation delays can be defined with the functions

Using these definitions and expressing 'on' resistance in terms of transistor sizes lead to [23]

where C_ox is unit capacitance of silica layer, µ_p/n is mobility of carriers, and (W/L)_p/n denotes sizes of concerned transistors. Derivation of equation (32) assumes an insignificant transition time for the driving signal at the input of the delay-block. In contrast, wideband pulses spend a finite amount of time to rise or fall at the input node and after this transition time is designated as t_up/down, corresponding delay equations at the output port will be modified as

Therefore, the final expression of inverter-delay for an individual gate will take the form of

If C_shunt accounts for only design values of intermediate capacitors, external loading capacitance from a following RF component is modeled as C_extra, input gate capacitance of the delay-block is defined with C_gate, and equation (28) is modified as

where y (1 for a 90 nm process) is a process-dependent proportionality factor. For an M-inverter N(=)-stage delay-block branch, the final expression will look like [23]

where F is overall effective fan-out of the delay unit. The power penalty suffered by a CMOS delay-block is expected to have three major components [24]. They include a dynamically dissipated power element (P_dynamic) arising from movement of charge through the shunt capacitor C_shunt at a switching frequency of f_op, a short-circuit power (P_sc) component consumed when both transistors in an inverter gate are on simultaneously with a peak current I_max and conduction duration t_on, and a static power (P_static) element dissipated by reverse leakage current I_rev.leak. The overall power figure for a complete wideband delay-block will depend on number of stages used in the delay chain sections, optimized rail voltage, intermediate capacitance, and finger width of devices. After being processed by the delay-block, the received signal will leave the front-end and be fed to the following radio-frequency mixer in the TR-receiver.

V. RESULTS AND DISCUSSION

The proposed receiver blocks are designed with an RF simulator including layout parasites generated by 90 nm circuit components to facilitate accurate RF analysis.

A. Wideband Differential Front-end

As the first section of the proposed TR-receiver front-end, the design parameters of the differential wideband low noise amplifier are analyzed with the CMOS process. The 90 nm amplifier is able to achieve high small signal gain and keep noise ceiling and power penalty below 3 dB and 15 mW, respectively. During parameter extraction, the LNA is interfaced with balun-circuits and a matched 50 load.

1) Forward Gain and Port-Reflection Parameters: The peak voltage gain (PVG) of the differential low noise amplifier with an open-circuited load-port is 20.4 dB in the K-band (24.5 GHz) and 18.1 dB at the center frequency (21.6 GHz), as shown in Fig. 5(a). It also shows that resistance to reverse isolation (S₁₂) is always greater than 28.3 dB and can reach up to 35 dB within the message bandwidth. In Fig. 5(b), maximum forward gain (indicated by S₂₁) is 11 dB, peaking at 21.6 GHz and presenting a 3-dB-bandwidth of 6.2 GHz (18.1-24.3 GHz). The same frame plots input and output port matching parameters (S₁₁ & S₂₂) with minima at -32 dB and -20.2 dB, respectively, in the 21-22 GHz range. The port return loss at the amplifier peak frequency (21.6 GHz) are -25.6 dB and -18 dB, in that order. Therefore, undesirable port-reflection remains insignificant over the concerned frequencies for the amplifier.

2) Estimation of Linear Behavior from the Amplifier: As the power of its driving signal (in dB_m) is raised for the wideband amplifier, the input-referred one-decibel compression point (1dB-CP ) is eventually crossed at -7.24 dB_m and the projection modeling the third-order intercept point (IIP₃) intersects the input power axis at 2 dB_m before the amplifier enters a non-linear region of gain compression (see Fig. 6). At the compression point the amplifier is expected to deliver 2 dB_m power to a matched load while still remaining in linear domain and the estimated output power at IIP₃ point is 12 dB_m.

3) Noise: With the employment of a differential topology, the designed front-end is able to maintain its noise parameters below the ceiling of 3 dB (2.58-2.97 dB). Its projected noise figures (NF and theoretical NF_min) are documented in Fig. 7(a) which coincide around the center point. NF settles around 2.58 dB near the center frequency (21.6 GHz) and approaches a minimum peak of 2.5 dB at the edge of its bandwidth, indicating optimum noise performance over this frequency coverage.

4) Power Gain and Power Penalty: Among an amplifier's power gain parameters, available gain (GA) provides an estimation of power gain provided by the core amplifier which is lowered down to transducer gain (GT) after the addition of port-matching networks. In Fig. 7(a), GA, GT, and GP (average power gain) coincide near 11 dB around the center frequency which can be interpreted as an indication of successful port-matching. Maintaining its compatibility with low power on-chip transceivers, dc power consumed by the font-end is measured as 13.9 mW when amplifier half-circuits and bias circuitry are powered with 5.72 and 0.2 mA currents, respectively.

5) Estimation of Stability (K_fand B_1ffactors): The amplifier is expected to be behave in an unconditionally stable manner over all frequencies around the message bandwidth. To assess this quality, the microwave stability factor B_1f is defined in terms of scattering parameters

which is required to satisfy the following condition

When presented in Fig. 7(b), B_1f is found to have a magnitude between 0.524 and 0.97 in the concerned range of bandwidth (18.1-24.3 GHz). To verify this result with a second stability parameter, the Rollett stability factor (K_rollet) is also plotted in the same figure with its value always being greater than a unit limit (fulfilling its criterion of stability) [13]. This factor is also defined with s-parameters

and has a relatively flat profile (3.71-3.82) with a lowest trough of 3.707 at 21.6 GHz. As a result, the amplifier will provide resistance to oscillation induced by white noise which may get accumulated in the circuit during its start-up mechanism.

B. Wideband Delay-Block (DB)

The proposed wideband delay-block (DB) to follow the front-end amplifier is also built with 90 nm CMOS devices as a part of the TR-receiver architecture. To illustrate the progression of a driving bipolar pulse stream through a multi-stage delay chain, a six-stage delay-block (built with the same principle presented in Fig. 4) is subjected to a pulse train of monocycle gaussian pulses. Fig. 8(a) presents the time domain signals existing at different nodes of the top section for a complete six-stage DB. Delayed versions (130-500 ps) of the positive half of the input pulse are collected from output nodes (m₁-m₆) of six successive stages (See Fig. 4) and a sample intermediate node (i₁) in the first stage of the delay chain. A symmetric balun produces identical replicas of the the driving pulse and feed them as sectional inputs (at points b and c). In Fig. 8(b), after the input pulse is elevated with a bias voltage (V_dd) for the bottom section, the driving signal is now collected from point d. Delayed versions for the elevated negative-half of the input signal show a progression of 150-650 ps at output nodes of stages in the bottom section (n₁-n₆). The final response (at node y) gathered after six stages in the bottom section is decoupled (dc component removed) at node w as shown in Fig. 8(c). It also shows the signal produced by the output combiner (culminating at node z) which manifests an average delay of 620 ps. Similar number of stages are employed in the DB branches to achieve identical and uniform delay for all pulse elements. The responses demonstrate that monotonic and quasi-linear rise in delay is available at output node of each of the six stages. To measure this phenomenon, (W/L)_p.(up/bot).q is selected as the notation to define dimension of individual transistors and C_p.int.q expresses value of a shunt DB capacitor where p=1-6 are stage indices of delay sections and q=1-4 indicate individual transistors or capacitors for a particular stage. To produce the response in Fig. 8, V_rail is set to 0.95 V and dimensions of the first stage are selected as

The other five stages require manipulation of device dimensions to compensate for any signal drop at intermediate nodes. Power dissipated by a single-stage delay-block is kept below 9 mW and for a six-stage delay unit power penalty reaches up to 10.6 mW. According to design requirement, number of stages in the DB can be varied to achieve regulated temporal shifts. The signal typically collected by a TR-receiver front-end is shown in Fig. 9(a) in the form of a wideband pulse stream made with monocycle gaussian pulses. Fig. 9(b) presents its delayed versions collected from the output ports of the proposed multi-stage delay-block. In addition to the number of stages in a DB section, tuning of delay may also be controlled by shunt capacitors, ratio of transistors, and magnitude of rail voltage [22]. This phenomenon is further illustrated in tabular form for a single-stage delay-block in the following section.

VI. SUMMARY OF PERFORMANCE

A. Front-End Amplifier

The synopsis of simulated performance extracted from the proposed differential front-end is summarized in Tables I and ^II where it is compared with simulated results of published wideband amplifier circuits [25]-[32]. To enable relative evaluation of amplifiers built on different scales of CMOS technology, a composite FOM (figure-of-merit) parameter is defined as

In summary, the proposed amplifier achieves a better figure of merit (10.5) and realizes a 22 GHz TR front-end customized for low-NF (2.6 dB) high-gain (11 dB) moderate power (13.9 mW) applications.

B. Delay-Block

The literature on the proposed delay-block has estimated that tuning of shunt capacitors and transistor dimensions will raise the group-delay achieved by the chain and increasing the rail voltage will have an opposite effect. To verify these predictions, performance of a single-stage delay-block under regulation is summarized in Table III where its specified controlling parameters (including number of cascaded stages) are varied. Among the four shunt capacitors of a single-stage DB, C_1.int.1 provides fine tuning (range of 50 ps) while other reactances are set to fixed values (C_1.int.3=C_1.int.1 and C_1.int.4=C_1.int.2=50 fF). Progression of bipolar peaks through the delay-block becomes non-uniform when device dimension is varied as their negative peak suffers from higher group dispersion. In Table III, W_1.up.1 and L_1.up.1 are manipulated as control figures for a delay variation of 150 ps when W_1.up.3=8 µm and W_1.up.2=W_1.up.4=16 µm. The third control parameter of the DB (rail voltage, V_rail) achieves a range of delay regulation which is nearly 200 ps. With total number of stages varying between one and eight, range of coarse adjustment for overall delay is measured as 180-790 ps. Power requirement for the delay-block has a fixed component (7 mW) for summer circuits and the remaining power element (peak) varies between 1.5 and 3.6 mW as eight stages are cascaded in both sections of the delay chain.

VII. CONCLUSIONS

This paper proposes circuit-level implementation of a 22 GHz 90 nm CMOS receiver front-end suitable for the principle of transmitted-reference (TR) communication. Using an LC port-matching technique, the front-end amplifier realizes a differential topology with high simulated gain (11 dB) to improve system noise performance (below 3 dB). Base NF ceiling for the wideband amplifier is expected to be 2.6 dB and the circuit consumes 13.9 mW when driven from a 1.2 V bias rail. Over its 6.2 GHz bandwidth, reverse isolation for the front-end is better than the margin of -28 dB with minimum port-matching parameters of -32 dB and -20.2 dB, respectively. A wideband 90 nm delay-block (DB) completes the CMOS front-end which is capable of producing a delayed version of the received pulse train. The dynamic DB circuit sections are extendable to eight stages and monotonic regulation of bipolar delay in the range of 70-800 ps is attained with four control parameters. Comparison with simulated reported designs establishes a superior figure-of-merit for the front-end amplifier and along with the delay-block it would complement the realization of a TR transceiver in circuit level.

VIII. ACKNOWLEDGMENT

The author would like to thank S. Rashid, Dr. H. Rashid, and the Dept of EEE of Bangladesh Univ. of Engineering and Technology.

Received 12 March 2013

For review 16 March 2013

Accepted 2 Apr 2013

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A passive-matched 22 GHz 2.6-dB-NF CMOS front-end with a 70-800 ps delay block

Apratim Roy

Publication Dates

• Publication in this collection
  27 Aug 2013
• Date of issue
  June 2013

History

• Received
  12 Mar 2013
• Accepted
  02 Apr 2013
• Reviewed
  16 Mar 2013