Novel Design of a Hybrid Superconducting Fault Current Limiter with Controlled Solid-State Device

Abstract

Fault current limiters are essential devices used to protect the power system and its equipment against high levels of fault current, which are growing up due to the increase of new power sources. This paper proposes a novel design of a Hybrid Superconducting Fault Current Limiter (Hybrid SFCL), which is composed basically by thyristors in series with a superconducting element. This branch is connected in parallel to an air-core reactor, which improves limitation and ensures the safe operation of the superconductor element. Another advantage of this topology is the use of the voltage drop in the superconductor as an input parameter to the controller. This voltage is used to detect the fault, which avoids the need for a current sensor and, consequently, reduces the manufacturing costs. In this work, the PSCAD/EMTDC software was employed to modeling the Hybrid SFCL and the 2G superconducting tape, which was modeled considering the thermal-electrical analysis. The results show that the fault current is efficiently limited, and the developed controller strategy has shown a relatively good performance. Furthermore, the proposed system guarantees a fast recovery time, in the order of 500 ms, which is a good advantage when compared to the conventional resistive SFCL.

Index Terms
Fault current limiter; Power system protection; Substation protection; Superconducting materials

I. Introduction

With the integration of new power generation systems, including renewable energy sources in the distribution system, the short-circuit level has increased. Furthermore, the power generation is not growing proportionally to the demand, which leads the system to operate close to its capacity limits [ ¹ ]–[ ⁴ ]. These conditions may result in fault situations that exceed the scaled levels for equipment that compose the electrical power system. One way to solve this problem is to scale up all the distribution substations, by replacing the main equipment, such as power transformers, protection systems, and automatic recloser. However, this solution can be too expensive and, in most cases, is not applicable. A more efficient and interesting solution is to use a Fault Current Limiter (FCL) [ ⁵ ]–[ ⁸ ], which reduces the fault current levels to a suitable value, thus avoiding the need to scale up the substation [ ⁹ ]–[ ¹¹ ]. The FCL is capable of operating with negligible impedance during normal system conditions, and during a fault event, it changes to a high resistive value in normal state, limiting the current to a reduced value.

The ideal characteristics of an FCL are: fast acting current limiting device, reduced recovery time, operating reliability, lower installation and maintenance costs, low loss and negligible impedance in normal operation, and a reduced volume and weight [ ¹² ].

Among the technologies found in the literature [ ¹² ], the Solid-State Fault Current Limiter (SSFCL) [ ¹³ ], [ ¹⁴ ] is presented as a promising solution for the application in power distribution systems. The SSFCL can be classified into three main groups [ ¹⁴ ]: series type [ ¹⁵ ], bridge type [ ⁷ ], [ ¹⁶ ], and resonant type [ ⁴ ].

Another solution that has been recently studied and experimentally applied is the Superconducting Fault Current Limiter (SFCL) [ ¹⁷ ]–[ ¹⁹ ]. Based on second generation (2G) of superconducting tapes [ ¹⁷ ], the resistive SFCL has the simplest and most compact structure, among other topologies [ ²⁰ ]–[ ²² ]. The main disadvantage of resistive SFCL is that the superconducting material takes a few seconds to recover its initial state after the fault extinction due to its thermal characteristics. Because of this fact, many works have been proposed trying to reduce the recovery time in resistive SFCL [ ²³ ], [ ²⁴ ].

To combine the advantages of the two topologies mentioned above, a Hybrid SFCL has been proposed and studied by different works [ ²⁵ ]–[ ²⁷ ]. The Hybrid SFCL topologies described by the references above are designed using superconducting elements and fast switches. The fast conventional switches are specially developed to act in the first cycle or half-cycle of the fault current [ ²⁶ ]. However, these switches have complex construction and a negative impact for reliability of this equipment [ ²⁸ ]. The topology proposed in this paper replaces the conventional fast switches by semiconductor ones, and the developed control algorithm uses the voltage drop that appears in the superconductor material during its thermal transition [ ²⁹ ]. Moreover, the use of voltage sensing aims to reduce the cost in the final price of the equipment, since the superconducting element transition indicates the occurrence of a fault event.

For this study, the Hybrid SFCL was simulated in PSCAD/EMTDC software. The 2G tape was modeled using a thermal-electrical approach, and it was validated comparing to the results with the experimental results found in previous work [ ³⁰ ].

This article is organized into five sections. After the introduction presented here, Section II presents the proposed Hybrid SFCL topology and its modeling. Section III and IV show the simulated cases and results, respectively. Finally, in Section V, the conclusion is presented.

II. Hybrid SFCL Topology

Hybrid SFCLs are normally composed of a superconducting material, a switching component (it may be a fast switch or a solid-state device), and a shunt component to limit the fault current and dissipate the power. The combination of the superconducting material and the solid-state switch device (thyristors, in the case of this work) in the same equipment can keep the advantages of each technology and avoid the problems encountered in both.

The proposed Hybrid SFCL, shown in Fig. 1 , is composed of antiparallel thyristors in series with a 2G tape (variable resistance - R_tape). This branch is connected in parallel to an air-core reactor (L), which improves limitation and ensures the safe operation of the superconductor element.

Fig. 1
Simplified hybrid SFCL circuit in (a) the normal operation and (b) during fault conditions.

The operation of the proposed Hybrid SFCL is given, according to Fig. 1 , as follows. In steady-state, the system current flows through the thyristors and the superconducting element ( R_tape ), as shown in Fig. 1(a) . When the fault occurs, the current increases, and it starts the superconducting transition. During this process, a voltage drop appears in the superconductor material as fast as the current increases due to the intrinsic characteristics of these materials. The voltage drop is used as a control parameter for the thyristors, and they are commanded to open. Thereafter, the current derives to the shunt reactor, which limits the fault current, as showed in Fig. 1(b) . The voltage measurement is performed in the Hybrid SFCL terminals and its value compared to the limit values. When the threshold is exceeded, the thyristors receive the open command signal. However, due to the characteristics of this switch, it will open only when the current crosses the zero value. During this time, the fault current will circulate entirely through the superconducting element, which will be responsible for the limitation itself. Note that without the superconducting element, the fault current will not be limited during the first half-cycle, and the system may have some electromechanical stress problem.

In a previous work of the authors, the superconducting element used in the proposed Hybrid SFCL topology was studied [ ³¹ ], and it was simulated using the thermal-electrical analogy that can be found in references [ ¹⁹ ], [ ³⁰ ], [ ³² ]. As shown in [ ³³ ], the superconducting element was built using a 2G tape manufactured by Super Power Inc., 12 mm width, a critical current of 275 A at 77 K and a critical temperature of 92 K [ ³³ ]. The 2G tape is composed of four layers with different sizes and materials. The superconducting layer is composed by Yttrium Barium Copper Oxide (YBCO), which corresponds only to 10% of the total 2G tape (0.1 mm thickness). Two silver layers (just for covering and protecting the superconducting material) and a Hastelloy layer, which gives a mechanical stabilization to the final tape, compose the majority part of the tape.

For this work, the PSCAD/EMTDC software was chosen to simulate the Hybrid SFCL applied in a simplified system. For the 2G tape model, the thermal-electrical analogy is implemented using the FORTRAN programming language. Therefore, this model reproduces the thermal and electrical behavior of the superconductor element. Moreover, this software allows evaluating the limiter operation in an electrical network represented by its Thévenin equivalent.

A. Electrical Model

To determine the 2G tape electrical behavior, firstly, four variable resistors in parallel are considered, which represents each layer individually. All the resistances and other parameters like current, resistivity, and temperature, for example, have the subscript corresponding to the layer (n), as represented in Fig. 2 .

Fig. 2
Cross-section of the tape 2G YBCO and its electrical representation [ ¹⁹ ], [ ³⁰ ], [ ³² ].

The electrical resistivity of the materials has a linear behavior concerning the temperature, except for the YBCO when it is below its critical temperature (T_c= 92 K) since it shows a non-linear relation [ ³⁴ ]. The electrical resistivity functions in (Ω.m), of the silver and Hastelloy material, are described in equations (1) and (2) respectively, where T_1,4 and T₃ are the temperatures, in Kelvin, of each silver layer (layers 1 and 4) and the Hastelloy layer (layer 3).

(1) $${\rho }_{1,4}=\left(-2,082•{10}^{-7}\right)+(6,17•{10}^{-9}•T_{1,4})$$

(2) $${\rho }_3=\left(-1,103•{10}^{-7}\right)+(8,958•{10}^{-9}•T_3)$$

The behavior of the YBCO electrical resistivity is different when the temperature is above or below T _c . At temperatures below T _c (T₂ ≤ T_c), the resistivity is a function of the electric field ( E ) and the current density ( J) , through a relation known as the E-J curve [ ³² ] and mathematically expressed in (3). At temperatures higher than T _c (T₂ > T_c), the YBCO electrical resistivity is a linear function of temperature, as expressed in ( 4 ).

(3) $${\rho }_2=E/J,(T_2\le T_c)$$

(4) $${\rho }_2=-0,1+\left({10}^{-2}•T_2\right),(T_2>T_c)$$

The electrical resistance of each layer is described in equation (5) , where d _n , l_n, and e_n are the length, width, and thickness of the n-layer, respectively. The calculation of the equivalent resistance R_{tap e} is expressed in equation (6) .

(5) $$R_n={\rho }_n•[d_n/(l_n•e_n)]$$

(6) $$\frac{1}{R_{tape}}=\left(\frac{1}{R_1}\right)+\left(\frac{1}{R_2}\right)+\left(\frac{1}{R_3}\right)+\left(\frac{1}{R_4}\right)$$

The expression for the current of each layer ( i _n ) is given by equation (7) , which can be obtained through a simple current divider, and i_tape is the total current flowing through the 2G tape.

(7) $$i_n=(R_{tape}/R_n)•i_{tape}$$

For the current calculation, the use of an iterative method is necessary, due to the non-linearity of the superconductor ( E-J relation) during its phase transition. Fig. 3 shows a flowchart summarizing the iterative process for calculating the electrical resistivity and the current in the superconducting element.

Fig. 3
Flowchart of the iterative process of resistivity and electric current in the superconductor. Adapted from [ ³⁰ ], [ ³² ].

For a current i_2(old) (step “a“) flowing through the superconductor, the YBCO temperature value T₂ is compared with T_c (step “b“). If T₂ is greater than T_c , then the material is in the normal state, wherein the resistivity of the YBCO layer is calculated using (4). The other resistivities are calculated using equations (1) and (2) , and the resistances through equations (5) and (6) , and the iterative process is finished (step “c”). Otherwise, if T₂ is smaller than T_c , the YBCO resistivity is given by equation (3) (step “d”), and the resistors R₂ and R_tape are updated by equations (5) and (6) , respectively (step “e“). The new value for the current flowing through the superconducting i_2(new) is calculated (step “f”), and the error between i_2(old) and i_2(new) is determined (step “g”); if the Error is less than the tolerance of 0.1%, it is considered stable, and the process ends. If it is higher than the tolerance, the i_2(old) value is incremented by a variable adjustment factor, which considers the Error behavior during the whole processes [ ³² ], and the iterative process will repeat until the Error is less than 0.1%.

B. Thermal Model

As mentioned before, to obtain the temperature of each layer at each step during the fault transient, a thermal-electrical analogy is proposed [ ³⁰ ], [ ³² ]. The fundamental purpose of this approach is to determine the variable electrical resistivity associated with the material temperature. Another advantage of this analogy comparing to the classical thermal equation is the simplicity to implement in PSCAD software, which improves the transient electrical calculation.

For this approach, it was considered that the temperature ( T _n ) varies only in one direction (1D) along with the thickness ( e _n ) of each layer of the 2G tape, as shown in Fig. 4 , wherein the T ₅ is the liquid nitrogen temperature (77 K). The temperature can be defined by the analogy between the 1D transient heat conduction equation, as shown in ( 8 ) (thermal variables), and the discrete RC circuit equivalent to the transmission line equation, in ( 9 ), with the equivalent electrical variables. The thermal-electrical circuit can be seen in Fig. 5 , wherein the source of DC voltage (77 V) represents the environment temperature, where the 2G tape is cooled by liquid nitrogen at 77 K (V₅).

(8) $$\frac{\partial T}{\partial t}=\frac{\lambda }{\gamma c}.\frac{{\partial }^{2}T}{\partial z^2}+\frac{g}{\gamma c}$$

(9) $$\frac{\partial v}{\partial t}=\frac{1}{R•C}.\frac{{\partial }^{2}v}{\partial z^2}+\frac{P}{R•C}$$

Fig. 4
Temperature variation within a cross-section of the superconducting tape layers. Adapted from [ ¹⁹ ], [ ³⁰ ], [ ³² ].

Fig. 5
Thermal-electrical equivalent for the 2G tape. Adapted from [ ¹⁹ ], [ ³⁰ ], [ ³² ].

Regarding the equation (8) , T is the 2G tape temperature, in Kelvin, t is the transient time (s), λ is the thermal conductivity at this point ( W / K . m ), z is the considered axis (m), γ is the specific mass of the material ( kg / m ³), c is the specific heat of the material ( J /( kg . K )), and g is the rate of internal heat generation into material ( W / m ³). Considering equation (9) , v is the voltage (V), R is the resistance (Ω), C is the capacitance (F), and P is the power (W) provided by the current source. It is noteworthy that the heats transfer along the x and y-axis were not considered, only the temperature gradient in each layer thickness along the z-axis. The current sources connected in parallel to the capacitor denotes the internal heat generation in each layer, highlighted in [ ³² ].

The following analogies for the electrical and thermal parameters, as shown in equations (10) to (13) , were considered. The electrical parameters such as the voltage (V_n), the conduction and convection resistance (R_{cond n} and R_conv), and the capacitance (Ca_n) represents, respectively, the following thermal parameters: temperature (T_n), the inverse thermal conductance, the convective transfer and the thermal capacity. Moreover, the current source value is given by the internal heat generation, which is expressed in terms of the electrical resistance (R_n), as written in equation (14) .

(10) $$V_n=T_n$$

(11) $$R_{condn}=l_n/({\lambda }_n•d_n•l_n)$$

(12) $$R_{conv}=1/(h_n•d_n•l_n)$$

(13) $$C{a}_n={\gamma }_n•c_n•d_n•l_n•e_n$$

(14) $$P_n=R_n•i_n^2$$

Applying Kirchhoff's law to the central nodes shown in Fig. 5 , it can be obtained the voltages values V₁ , V₂ , V_3, and V₄ and, consequently, the temperature values T₁ , T₂ , T_3, and T₄ .

C. Solid-State Device Modeling

Solid-state switches have some disadvantages compared to electromechanical ones, such as the need for an electronic control circuit and a power drive, and the losses presented in conducting state. However, their usage is justified by their superior performance and reduction of implementation and maintenance costs that give a better cost/benefit ratio. Regarding the proposed Hybrid SFCL simulation, the chosen solid-state switch (thyristor) is already modeled in PSCAD/EMTDC software.

III. Simulation

In this section, the superconducting element model is employed to validate the proposed Hybrid SFCL topology and its controller. This model was developed in PSCAD/EMTDC software as described in the previous section. Fig. 6 shows the circuit simulation with the components of Hybrid SFCL, which is composed in two main branches. The first one, called the superconducting element branch, is composed of the antiparallel thyristors in series with the 2G tape. The second one is the branch with the air-core reactor used to limit the fault-current (shunt element). This air-core reactor is modeled with a resistor and an inductor in series. To employ the Hybrid SFCL model in an electrical system, it was considered an equivalent 13.8 kV feeder based on a real distribution system, which has a load impedance and a fault impedance described in Table I . This scenario is the maximum fault current case, which has a first asymmetric peak current (I_p) around to 6.0 kA_peak and a symmetric current (I_s) around to 2.5 kA_rms. The air-core reactor was specified to reduce the prospective fault current in 60%, and the values in Table I were calculated as indicated in [ ³⁵ ].

Fig. 6
Proposed Hybrid SFCL simulation in PSCAD/EMTDC software.

Table I
Simulation parameters

Parameters	Values
Voltage	13.8	kVrms
Frequency	60	Hz
Load Impedance	107.75	Ω
	58.038	mH
Fault Impedance	0.579	Ω
	16.269	mH
Air Coil Impedance	0.965	Ω
	17.069	mH
Duration of run	1.0	s
Solution Time Step	10.0	μs
Channel Plot Step	10.0	μs

A. Superconducting Tape

Based on the statements presented in Section II.A., it is possible to model the thermal and electrical characteristics of the 2G tape. This model reproduces the tape behavior in both transient and steady-state conditions, which are necessary to study the Hybrid SFCL when submitted to a fault current. For the modeling, a new component was created in PSCAD/EMTDC ( Fig. 7 (a)) with its behavior is described by a FORTRAN code. This component has two input parameters, V_base and I_critic , which are the grid voltage base and the critical current of the 2G tape, respectively. The V_base is used to define the length of the tape. In this work, the line-to-line voltage base ( V_base ) is 13.8 kV, and the maximum electric field allowable for the 2G tape is 0.5 V/cm, as indicated in [ ³³ ]. As a result, approximately 160 m of superconducting tape is needed for the limiter. The critical current of selected 2G tape is 275 A.

Fig. 7
(a) Component created in PSCAD/EMPTDC to calculate the resistance of the superconducting tape and (b) variable resistance.

The FORTRAN code is processed at each time step with the following steps:

• Read the tape current $I_{sct}=I_{tape}$ (code input);

• Calculate the resistivity and electrical resistance of each layer, ρ _1,3,4 and R _1,3,4, according to ( 1 ), ( 2 ), and ( 5 ), except for the YBCO layer;

• The iterative process to calculate the resistivity of the superconductor material, its resistance, and current, ρ₂, R ₂, and i ₂, according to the flowchart of Fig. 3 ;

• Calculate R_tape , according to ( 6 );

• Calculate the thermal parameters of each layer based on the previous temperature, R_{cond n} , R_conv , ca_n and p_n , according to ( 11 ) until ( 14 );

• Calculate the current passing through the other layers, I_n , according to ( 7 );

• Calculate the temperature in each layer, T_n , based on the thermal-electrical analogy ( 10 ), were V_n is obtained through a matrix solution of the equivalent circuit shown in Fig. 5 .

The temperature T_n is calculated by applying the nodal analysis method in the circuit of Fig. 5 , and then determined a system of partial time differential equations. Since it is a system of coupled equations with more than one independent variable (temperature), as a function of the same independent variable (time), the Euler's method is applied for solving ordinary differential equations, as demonstrated in [ ³² ]. Furthermore, the implicit method is adopted with not minimal step-time ( dt ) to achieve numerical stability.

The output of the code is the value of the variable resistor (R_tape), depending on the current flowing through it (I_sct), both depicted in the equivalent circuit of Fig. 7 (b). It is important to highlight that the temperatures of the layers need an initial condition to be defined by the user. In this work, they are set at 77 K for all layers. Therefore, the variables used for calculation in each step are based on the previously calculated values in the current step or the values defined in the previous step.

For validation purposes, the results of the superconducting tape model obtained in this study were compared to the results in [ ³⁰ ], [ ³² ], which were validated based on experimental tests of the tape. The simulation results of the tape converge to the same values, and then this is enough to validate the model developed in PSCAD/EMTDC. In this way, subsequent simulations of the Hybrid SFCL can be carried out assuming suitable behavior of the tape in both transient and steady-state conditions. These validation results are not presented here because they are not the main aim of the study.

B. Hybrid SFCL Control

Fig. 8 shows the triggering circuit for firing the thyristors used in the proposed Hybrid SFCL topology. The control works as follows: the voltage between the limiter terminals ( E_FCL ) is compared to a predetermined threshold in block “A”. If E_FCL cross the threshold value, the limiting mode is activated, and the gate signal is set to low-state to order switching off. To restore the normal operation, besides the condition of E_FCL lower than the threshold value, a time delay is imposed to ensure that the superconducting material returns to 77 K. A logical operator (AND) and a time delay block (block “B”) are used to provide such functionality, as shown in Fig. 8 .

Fig. 8
Switching control.

The threshold is defined according to the peak-voltage of the limiter operating in the limiting mode, within the minimum value obtained in the presence of a fault and the maximum value obtained after the fault is cleared. This range avoids the improper operation due to overvoltage and ensures the transition to the normal mode when the fault is cleared. The aforementioned values are obtained through simulations considering the possible variation of the system parameters. In this work, the minimum peak-voltage of the limiter operating in the limiting mode and in the presence of a fault is 10.0 kV. The maximum peak-voltage of the limiter operating in the limiting mode and after the fault is cleared is 1.2 kV. The threshold value is set as 2.0 kV.

IV. Results

A. Currents in Hybrid SFCL

Fig. 9 shows the simulation results for a fault at 0.1 s. In this figure, the green curve is the prospective curve (fault current without the limiter); the blue curve is the limited curve; the red curve is the current through the thyristor and 2G tape branch, and; the pink curve indicates the gate triggering, i.e., control order to the limiter. The red curve shows the main advantage of the proposed topology. As the superconducting element transits in a fault condition, the fault current is already limited before passing through the air-core reactor branch (less than a quarter of half-cycle). Hence, the thyristor can switch off before the end of first half-cycle of limited current (blue curve). Therefore, the first peak of the limited current is 2.89 kA_peak, which represents a 51.56%reduction from the 5.61 kA_peak prospective curve. The steady-state current shows 1.58 kA_peak for the limited current, which represents a 47.13%reduction from the 3.35 kA_peak prospective curve.

Fig. 9
Currents in hybrid SFCL.

The association of the instantaneous current limitation provided by the superconducting element with the faster switching off provided by the thyristors, the proposed topology enhances the FCL performance when compared with both conventional SFCL and SSFCL. The superconducting element transition enables a current limitation in the first half-cycle, overcoming the limitation of the solid-state FCL topology due to the thyristor switching characteristic. The thyristors’ operation after the end of fault current half-cycle protects the 2G tape, in the superconducting element branch, to be exposed at long time high-level currents and then ensuring increased durability and faster recovery time.

It is important to note that the proposed controller ensure that the fault current is clear, and the 2G tape lies in the superconducting state before switching on the thyristors to operate the limiter in the normal mode again. This is the reason for the control signal was applied only at 0.61 s.

B. Control Analysis

In Fig. 10 , the relationship between fault current and the voltage used for controlling the switches is presented. In this study, the voltage threshold is set at 2 kV. When this threshold is reached, the instantaneous current flowing through the limiter is approximately 672 A. This current is higher to the nominal current of 13.8 kV feeder (125 A_rms) being considered as a fault-current level. At 0.2 s the fault is extinguished, and the voltage level is again below the threshold. However, the superconducting element has to recover from the transition. In this way, a 500 ms delay is imposed to ensure the recovering process.

Fig. 10
The controlling relationship between current and voltage.

In the graph, the orange curve is the voltage at the limiter that switches from 10.1 kV to 1.2 kV, considering the parameters mentioned in this work and the driver acting range explained in Section III.B.

C. The Temperature of the Superconducting Element

Since the superconducting element has been modeled concerning the electrical and thermal characteristics, it is possible to obtain the temperature rise of each layer by simulation, as showed in Fig. 11 . It was observed that the temperature reaches 95.86 K and as soon as the fault was cleared, a fast temperature reduction occurs due to the opening of the superconducting element branch. Hence, the superconducting element takes about 500 ms to return to the steady-state (77 K). This is the time delay necessary to ensure the material return to the superconducting state, applied in the control to restore the normal operation even if the fault is already cleared.

Fig. 11
Temperature rise of each of the superconducting layer - using thyristors.

D. Comparison Between the Proposed Hybrid SFCL and Conventional SFCL

To evaluate the benefits of the proposed topology comparing to the conventional SFCL, the thyristors were replaced by an ideal circuit breaker with an open time delay. This delay was used to emulate the time of mechanical circuit breakers, set at 50 ms [ ³⁶ ]. For the control system, the same logical proposed in this paper was used. In Fig. 12 , the first peak remains to the same behavior as observed in Fig. 11 since the superconducting element transits to the normal state. The difference is evident after the first peak. Because the time delay to clear the fault current at the superconducting element branch, the superconductor temperature lies above the critical temperature (92 K). This high temperature may require a higher length of 2G tape and reduces its lifetime when compared to the proposed topology.

Fig. 12
Temperatures of the superconducting layers - Limiter with emulated mechanical switch.

In Fig. 13 , the limited curves are compared. Until the thyristor switches off, both limited curves have the same behavior since the current is through in the superconducting element and the air-core reactor. After the thyristors open, only the air-core reactor is limiting the current in the proposed Hybrid SFCL, whereas the conventional SFCL takes about 50 ms to open. Thereafter, they return to exhibit the same limited current behavior. It noted that the high superconducting resistance in the normal state make the difference between these two topologies not huge. Nevertheless, other effects like electrical arcing by opening a conventional circuit breaker, mechanical stress and the power dissipation in the 2G tape must be considered.

Fig. 13
Limited current using thyristors and emulated mechanic switch.

V. Conclusion

This paper proposed a Hybrid SFCL topology to enhance the limiting performance and to combine the benefits of the SFCL and the SSFCL. The control is based on the measured voltage at the terminals of the limiter, so a voltage sensor is possible to applied due to the transition of states of the superconducting element. The voltage drop along the 2G tape occurs when the current is above its critical value (e.g., a fault condition). This transition results in an increased voltage at the limiter terminals. Hence, it avoids the need for a current sensor that could be more expensive than the proposed sensor. The hybrid topology provides a faster opening of the superconducting element branch, which reduces its recovery time, avoids the need for a huge 2G tape length, and improves its lifetime.

The superconducting element was modeled in PSCAD/EMTDC software. This model considered the thermal-electrical characteristic of the 2G tape. The simulation results with the proposed Hybrid FCL showed that the fault current is limited less than a quarter of half-cycle, even using the thyristors. This is possible because the current in the superconducting element branch is already limited before flowing through in the air-core reactor branch, which represents the majority of the limited current. The proposed limiter was compared with a conventional SFCL using an emulated electromechanical circuit breaker. Simulation results showed that the proposed Hybrid FCL has a better performance in the transient condition of the fault.

Acknowledgment

This work was supported in part by the Light Electricity Services S/A by the ANEEL R&D program. The authors would like to thank the CNPq, INCT CNPq-INERGE, CAPES, and FAPERJ for their financial support.

REFERENCES

• ^[1]
  A. Colmenar-Santos, J. M. Pecharromán-Lázaro, C. de Palacio Rodríguez, and E. Collado-Fernández, “Performance analysis of a Superconducting Fault Current Limiter in a power distribution substation,” Electr. Power Syst. Res ., vol. 136, pp. 89–99, Jul. 2016.
• ^[2]
  M. Ahmadvand, S. Khanabdal, and M. T. Hagh, “A Novel Three-Phase Saturable-Core Fault Current Limiter Structure,” IEEE Trans. Power Deliv. , vol. 34, no. 2, pp. 410–419, Apr. 2019.
• ^[3]
  L. M. Castro, D. Guillen, and F. Trillaud, “On Short-Circuit Current Calculations Including Superconducting Fault Current Limiters (ScFCLs),” IEEE Trans. Power Deliv ., vol. 33, no. 5, pp. 2513–2523, Oct. 2018.
• ^[4]
  A. N. R. L. Sirisha and A. K. Pradhan, “Parameter Estimation of Resonant Fault Current Limiter for Protection and Stability Analysis,” IEEE Trans. Power Syst. , vol. 32, no. 3, pp. 2288–2295, May 2017.
• ^[5]
  M. Eladawy and I. A. Metwally, “Design and Performance Analysis of Single-Phase Pre-Saturated Core Fault Current Limiters,” IEEE Trans. Power Deliv ., vol. 33, no. 6, pp. 2603–2612, Dec. 2018.
• ^[6]
  A. Abramovitz, K. M. Smedley, F. De La Rosa, and F. Moriconi, “Prototyping and Testing of a 15 kV/1.2 kA Saturable Core HTS Fault Current Limiter,” IEEE Trans. Power Deliv. , vol. 28, no. 3, pp. 1271–1279, Jul. 2013.
• ^[7]
  H. Radmanesh and S. H. Fathi, “Fast AC reactor-based fault current limiters application in distribution network,” High Volt. , vol. 3, no. 3, pp. 232–243, Sep. 2018.
• ^[8]
  B. Vyas, R. P. Maheshwari, and B. Das, “Protection of series compensated transmission line: Issues and state of art,” Electr. Power Syst. Res. , vol. 107, pp. 93–108, Feb. 2014.
• ^[9]
  T. Ghanbari and E. Farjah, “A Multiagent-Based Fault-Current Limiting Scheme for the Microgrids,” IEEE Trans. Power Deliv. , vol. 29, no. 2, pp. 525–533, Apr. 2014.
• ^[10]
  C. Meyer, P. Kollensperger, and R. W. De Doncker, “Design of a novel low loss fault current limiter for medium-voltage systems,” in Nineteenth Annual IEEE Applied Power Electronics Conference and Exposition , 2004. APEC ’04., Anaheim, CA, USA, 2004, vol. 3, pp. 1825–1831.
• ^[11]
  D. Guillen, et al., “Impact of Resistive Superconducting Fault Current Limiter and Distributed Generation on Fault Location in Distribution Networks,” Electric Power Systems Research , vol. 186, pp.106419, May. 2020.
• ^[12]
  M. Noe and M. Steurer, “High-temperature superconductor fault current limiters: concepts, applications, and development status,” Supercond. Sci. Technol. , vol. 20, no. 3, pp. R15–R29, Mar. 2007.
• ^[13]
  H. Radmanesh, S. H. Fathi, G. B. Gharehpetian, and A. Heidary, “A Novel Solid-State Fault Current-Limiting Circuit Breaker for Medium-Voltage Network Applications,” IEEE Trans. Power Deliv. , vol. 31, no. 1, pp. 236–244, Feb. 2016.
• ^[14]
  A. Abramovitz and K. Ma Smedley, “Survey of Solid-State Fault Current Limiters,” IEEE Trans. Power Electron. , vol. 27, no. 6, pp. 2770–2782, Jun. 2012.
• ^[15]
  C. Meyer, P. Kollensperger, and R. W. De Doncker, “Design of a novel low-loss fault current limiter for medium-voltage systems,” in Nineteenth Annual IEEE Applied Power Electronics Conference and Exposition , 2004. APEC ’04., Anaheim, CA, USA, 2004, vol. 3, pp. 1825–1831.
• ^[16]
  M. A. H. Sadi and Mohd. H. Ali, “Transient stability enhancement by bridge type fault current limiter considering coordination with optimal reclosing of circuit breakers,” Electr. Power Syst. Res. , vol. 124, pp. 160–172, Jul. 2015.
• ^[17]
  G. dos Santos, A. A. Bitencourt, A. T. Queiroz, F. G. R. Martin, F. Sass, D. H. N. Dias, G. G. Sotelo, and A. Polasek. “Tests and recovery under load simulations of a novel bifilar resistive SFCL having undulated shape configuration,” Superconductor Science and Technology , vol. 34, pp. 1-22, Jan. 2021.
• ^[18]
  S. S. Kalsi and A. Malozemoff, “HTS fault current limiter concept,” in IEEE Power Engineering Society General Meeting , 2004., Denver, CO, USA, 2004, vol. 2, pp. 1426–1430.
• ^[19]
  G. R. F. Q. Mafra, G. G. Sotelo, M. Z. Fortes, and W. T. B. de Sousa, “Application of resistive superconducting fault current limiters in offshore oil production platforms,” Electr. Power Syst. Res. , vol. 144, pp. 107–114, Mar. 2017.
• ^[20]
  J. Bock et al., “HTS Fault Current Limiters—First Commercial Devices for Distribution Level Grids in Europe,” IEEE Trans. Appl. Supercond. , vol. 21, no. 3, pp. 1202–1205, Jun. 2011.
• ^[21]
  J. S. Lamas, C. A. Baldan, C. Y. Shigue, A. Silhanek, and V. Moshchalkov, “Electrical and Magnetic Characterization of BSCCO and YBCO HTS Tapes for Fault Current Limiter Application,” IEEE Trans. Appl. Supercond. , vol. 21, no. 3, pp. 3398–3402, Jun. 2011.
• ^[22]
  A. Pellecchia et al., “Development of a Saturated Core Fault Current Limiter With Open Magnetic Cores and Magnesium Diboride Saturating Coils,” IEEE Trans. Appl. Supercond. , vol. 27, no. 4, pp. 1–7, Jun. 2017.
• ^[23]
  W. T. B. de Sousa, F. N. F. Dicler, and F. G. dos R. Martins, “Simulations of the Recovery Process of an Air-Coil SFCL,” IEEE Trans. Appl. Supercond. , vol. 26, no. 1, pp. 1–6, Jan. 2016.
• ^[24]
  W. T. Batista de Sousa, T. Mariano Lessa Assis, A. Polasek, A. M. Monteiro, and R. de Andrade, “Simulation of a Superconducting Fault Current Limiter: A Case Study in the Brazilian Power System With Possible Recovery Under Load,” IEEE Trans. Appl. Supercond. , vol. 26, no. 2, pp. 1–8, Mar. 2016.
• ^[25]
  S. M. Alaraifi and M. S. El Moursi, “Hybrid HTS-FCL Configuration With Adaptive Voltage Compensation Capability,” IEEE Trans. Appl. Supercond. , vol. 24, no. 6, pp. 1–8, Dec. 2014.
• ^[26]
  O.-B. Hyun et al., “Long-Term Operation and Fault Tests of a 22.9 kV Hybrid SFCL in the KEPCO Test Grid,” IEEE Trans. Appl. Supercond., vol. 21, no. 3, pp. 2131–2134, Jun. 2011.
• ^[27]
  Ok-Bae Hyun, Kwon-Bae Park, Jungwook Sim, Hye-Rim Kim, Seong-Woo Yim, and Il-Sung Oh, “Introduction of a Hybrid SFCL in KEPCO Grid and Local Points at Issue,” IEEE Trans. Appl. Supercond. , vol. 19, no. 3, pp. 1946–1949, Jun. 2009.
• ^[28]
  Ok-Bae Hyun, Jungwook Sim, Hye-Rim Kim, Kwon-Bae Park, Seong-Woo Yim, and Il-Sung Oh, “Reliability Enhancement of the Fast Switch in a Hybrid Superconducting Fault Current Limiter by Using Power Electronic Switches,” IEEE Trans. Appl. Supercond. , vol. 19, no. 3, pp. 1843–1846, Jun. 2009.
• ^[29]
  Y. Y. Xie, K. Tekletsadik, D. Hazelton, and V. Selvamanickam, “Second Generation High-Temperature Superconducting Wires for Fault Current Limiter Applications,” IEEE Trans. Appl. Supercond. , vol. 17, no. 2, pp. 1981–1985, Jun. 2007.
• ^[30]
  A. T. Queiroz et al., “Simulation of resistive superconducting fault current limiter in ATPDraw,” in 2018 Simpósio Brasileiro de Sistemas Eletricos (SBSE) , Niterói, 2018, pp. 1–5.
• ^[31]
  A. Morandi, “State of the art of superconducting fault current limiters and their application to the electric power system,” Phys. C Supercond ., vol. 484, pp. 242–247, Jan. 2013.
• ^[32]
  W. T. B. de Sousa, A. Polasek, R. Dias, C. F. T. Matt, and R. de Andrade, “Thermal–electrical analogy for simulations of superconducting fault current limiters,” Cryogenics , vol. 62, pp. 97–109, Jul. 2014.
• ^[33]
  S. Elschner et al., “ENSYSTROB-Resistive Fault Current Limiter Based on Coated Conductors for Medium Voltage Application,” IEEE Trans. Appl. Supercond. , vol. 21, no. 3, pp. 1209–1212, Jun. 2011.
• ^[34]
  M. K. Wu et al., “Superconductivity at 93 K in a new mixed-phase Y-Ba-Cu-O compound system at ambient pressure,” Phys. Rev. Lett. , vol. 58, no. 9, pp. 908–910, Mar. 1987.
• ^[35]
  M. F. de Souza, A. T. Queiroz, G. G. Sotelo, P. R. Monteiro, M. Z. Fortes, and A. Polasek, “Fault current limiters: a case study of protection and operational continuity for FPSOs,” Electrical Engineering , vol. 1, pp. 1-11, Feb. 2021.
• ^[36]
  “Schneider Electric, Evolis 24kV catalogue, AMTED307011EN, FEB. 2014.”

Publication Dates

• Publication in this collection
  18 June 2021
• Date of issue
  June 2021

History

• Received
  01 Sept 2020
• Reviewed
  16 Sept 2020
• Accepted
  11 Apr 2021