Poly(Vinyl Alcohol) Gate Dielectric Treated With Anionic Surfactant in C₆₀ Fullerene-Based n-Channel Organic Field Effect Transistors

Abstract

We report on the preparation and performance enhancement of n-type low-voltage organic field effect transistors (FETs) based on cross-linked poly(vinyl alcohol) (cr-PVA) as gate dielectric and C₆₀ fullerene as channel semiconductor. Transistors were prepared using bottom-gate top-contact geometry and exhibited field-effect mobility (µ_FET) of 0.18 cm²V^-1s^-1. Treatment of the gate dielectric surface with an anionic surfactant, sodium dodecyl sulfate (SDS), passivates the positively charged defects present on the surface of cr-PVA, hence resulting in overall transistor performance improvement with an increase in µ_FET to 1.05 cm²V^-1s^-1 and additional significant improvements in dielectric capacitance, transistor on/off current ratio and transconductance.

Keywords
organic field-effect transistors; C₆₀; poly(vinyl alcohol); surfactant

1. Introduction

Organic field effect transistors (FETs) have been a subject of much research over the past few decades due to the great technological up burst towards flexible organic electronics. However, n-type FETs were less investigated^1-3 than p-type ones, in part because of their unstable nature and high sensitivity to humidity and oxygen.^4,5 Nevertheless, owing to the importance of commercial applications involving organic complementary logic circuits, both p- and n-type FETs are in principle required.⁶

In the last years many results of high-mobility C₆₀-based field effect transistors have been reported exploiting single crystals, ensuing expensive techniques and methods,^3,7-9 or either preparing devices that are eventually not compatible with flexible substrates.^10,11 In this context, in addition to enhanced performance, cost-effectiveness, simplicity of device preparation and compatibility with flexible substrates is highly desired.

The use of cross-linked poly(vinyl alcohol) (cr-PVA) as gate dielectric in transistors is a topic showing intense research activity^12-16 and there are strong evidences that the surface of cr-PVA consists of negatively and positively charged defects that act as charge traps or scattering centers and hinder charge flow near the insulator/semiconductor (I/S) interface. Transport hindrance is to a great extent imposed by the topology of the equipotential electrostatic surface near the I/S interface instead of being simply due to the surface morphology. In this context, passivation/neutralization of such traps is necessary to ameliorate device performance. Treatments have recently successfully solved this problem in devices based on p-type channel semiconductors, poly(3-hexylthiophene-2,5-diyl)^17-19 and copper phthalocyanine.^20,21 As transistor size gets smaller, many undesirable effects come into play and nanometrically small defects and traps play a significant role, impairing device performance.

In a grounded-source FET, the gate voltage V_GS aims the accumulation of mobile charges at the vicinity of the I/S interface, while the drain voltage V_DS is applied to promote the charge transport along the channel. Due to the simultaneous application of both voltages, the thickness of the effective channel (region of the channel effectively participating in the charge transport process) varies along the channel. It shows a minimum, denoted channel bottleneck, near to the source terminal. Thus, since this bottleneck is adjacent to the I/S interface, the performance of the FET is limited due to the hindering of charge transport by the cr-PVA surface traps, which is evidenced if charge-carrier field-effect mobility (µ_FET) is plotted as a function of channel bottleneck thickness (l₀).²⁰

In this work we report on the preparation of transistors with a solution-processed flexible substrate compatible organic gate dielectric, cr-PVA and C₆₀ channel semiconductor. In addition, we show an easy and cost-effective method to suppress the action of negative charge traps present on the surface of cr-PVA using the deposition of an anionic surfactant, sodium dodecyl sulfate (SDS), in turn obtaining an enhanced transistor performance. To get a better insight regarding the charge transport we support our discussion by showing the variation in µ_FET with respect to l₀, which provides important information regarding the variation of µ_FET as a function of distance from the I/S interface.

2. Experimental Procedure

Device fabrication and characterization procedures are reported in detail in Ref.²¹ Briefly, Al gate was evaporated onto glass substrate and PVA was thermally and UV treated to obtain cross-linked PVA (cr-PVA) after which Al layer was covered by spin-coating cr-PVA on top of it. SDS (supplied by Sigma-Aldrich, ACS Reagent > 99%) was dissolved in water at a concentration of 3.0 mg/mL and stirred for one hour at 60ºC. A ~20 nm SDS layer was then spin-coated on the Al/cr-PVA films at 1500 rpm for 60 s and sequentially annealed in vacuum for 30 min at 100ºC followed by C₆₀(Sigma-Aldrich, 99.5%) layer deposition. C₆₀ was thermally evaporated using shadow mask to control the layer geometry. Shadow mask patterned gold was then evaporated to obtain source and drain terminals. Devices were then encapsulated using 4.5 mg of PIB (polyisobutene, molecular mass: 850-900 g/mol, density: 0.88 mg/mm³, viscosity: 2.5 × 10⁵ SUS at 21ºC, supplied by Polibutenos S.A Indútrias Químicas) that was dropped onto the device area and covered with a 0.1 mm thick glass slice, as detailed reported by Toniolo et al.²² Transistor structure and chemical structure of C₆₀ are shown in Figure 1.

Figure 1
(a) Schematic structure of the SDS-treated OFET, (b) chemical structure of C₆₀, and; (c) chemical structure of SDS.

Capacitance measurements were performed in Al/cr-PVA/Au and Al/cr-PVA/SDS/Au sandwich structures using an Agilent 4284-A LCR meter, at a frequency of 1 kHz. Transistor characterization was carried out using a Keithley 2602 dual source meter in air in the dark.

3. Results and Discussions

Charge transport in OFETs is governed by several mechanisms, including the amount of charge accumulated at the I/S interface following appliance of a potential between gate and channel semiconductor. Once drain-source voltage (V_DS) is applied, an electric field along the x-direction results in the transport of charge along the channel from source to drain (Figure 2). The drain-source current (I_DS) is expressed in saturation regime (V_DS>V_T) as:

(1) ${\mathit{I}}_{\mathit{DS}}=\frac{\mathit{W}{\mathit{\mu }}_{\mathit{FET}}{\mathit{C}}_{\mathit{i}}({\mathit{V}}_{\mathit{GS}}-{\mathit{V}}_{\mathit{T}}{)}^2}{\mathit{2}\mathit{L}}$

where W is the channel width, µ is the field-effect charge carrier mobility, V_GS is the applied gate voltage, V_T is the threshold voltage and L is the channel length. Increasing V_GS restricts I_DS very close to the I/S interface, essentially reducing the effective channel thickness, and hence the very first few molecular layers of the interface determine the charge transport properties. The drift-diffusion equation allows estimating the minimum effective channel thickness (l₀) perpendicular to the I/S interface, along the z-direction,²³ in the effective channel bottleneck. It can be expressed as:

(2) ${\mathit{l}}_0=\frac{4\epsilon \mathit{kT}}{{\mathit{eC}}_{\mathit{i}}({\mathit{V}}_{\mathit{GS}}-{\mathit{V}}_{\mathit{T}})}$

where ε is the channel semiconductor dielectric constant, k is the Boltzmann constant, T is the absolute temperature, e is the electronic charge and C_i is the gate dielectric specific capacitance.

Figure 2
Schematic representation of FET showing the variation of effective channel thickness l along the x-direction, with the effective channel represented in gray.

Figure 3a shows the I_DS versus V_DS plots for the gate voltage V_GS varying between 0 and 5 V measured in samples with and without SDS-treated cr-PVA, for comparison. Similar to the behavior observed in conventional FETs with increasing V_DS, the I_DS initially increases linearly, then levels off gradually, and approaches a saturated value. The I_DS value is improved when cr-PVA layer is treated with SDS. One important aspect to be kept in mind while working with C₆₀ semiconductor is that, in general the n-type behavior of organic semiconductor is reasonably sensitive to physically and chemically adsorbed O₂ and/or H₂O molecules, which can possibly generate electron traps, hence suppressing the charge transport.^24-27 In order to protect the device from the adsorption of O₂ or H₂O molecules, the C₆₀ layer was encapsulated using PIB as described above.

Figure 3
(a) Output characteristics (I_DS(V_DS)) of SDS treated device (inset shows I_DS(V_DS) of untreated device) (open circles correspond to I_GS(V_DS)); (b) transfer characteristics (I_DS(V_GS)); (c) linear best-fit plots for mobility and V_T calculation (the curves are taken in the increasing V_GS regime), and; (d) transconductance (g_m) as a function of V_GS, for untreated and SDS treated devices.

The effective channel thickness bottleneck limits the charge transport because of the presence of charge traps or dipoles at the I/S interface owing to the surface of the gate dielectric.²⁸ This is then reflected in the form of low µ_FET and hence low I_DS as seen in the output characteristics, I_DS(V_DS) (Figure 3a). The surface of cr-PVA consists of charge traps and dipoles acting as charge trapping or scattering sites.^15,16 Our results indicate that the passivation of negatively charged centers on the cr-PVA surface results in enhancement of charge accumulation at the I/S interface, resulting in an increase in C_i, µ_FET, I_DS (Figure 3a) and transconductance, g_m ≡ dI_DS/dV_GS (Figure 3d). This seems to be contradictory to the observed displacement of V_T to a more positive value (Table 1). But as can be observed in Figure 3c, the slope of the curve depends on the V_GS range, as a consequence implying in a large uncertainty in the V_T value. For this same reason, the use of the transfer characteristics, I_DS(V_GS) (Figure 3b) and linear best-fit plot for mobility (Figure 3c) also depends on the V_GS interval, despite indicating a clear trend to higher mobility. It can clearly be seen that the deposition of SDS on top of the cr-PVA layer results in significant device parameters enhancement. SDS is assumed to be working as a part of the dielectric layer, as an extension of the gate dielectric, since when compared to the untreated devices, no increase in the OFF current of the SDS-treated ones is observed. Device parameters of both untreated and SDS-treated transistors are summarized in Table 1.

Table 1
Device performance parameters for untreated and SDS treated C₆₀-based n -type FETs. The g_m and g_m/W values were calculated at V_DS = 6 V.

Device	VT	μ (cm2 V-1 s-1)	Ci (nF cm-2)	Ion/Ioff	gm (μS)	gm/W (S cm-1)
cr-PVA only	2.76±0.30	0.18±0.15	15.18	70	0.17	8.50 × 10-7
SDS treated	2.96±0.10	1.05±0.08	25.38	565	0.81	4.05 × 10-6

The Dependence of µ_FET on V_GS and on l₀ can be determined in saturation regime (V_DS> V_T) (Figure 4) using²⁹

(3) ${\mathit{\mu }}_{\mathit{FET}}=\frac{2\mathit{L}}{{\mathit{WC}}_{\mathit{i}}}[\mathit{d}({\mathit{I}}_{\mathit{DS}}{)}^{1/2}/{\mathit{dV}}_{\mathit{GS}}{]}^2$

which gives direct information about the variation of mobility with respect to the different bottleneck thicknesses induced by V_GS. One important feature observed in the µ_FET vs.l₀ plot (Figure 4b) is that, apart from the magnitude of I_DS being higher, the shape of the curve is different. It can be seen in Figure 4a that µ_FET initially increases with increasing V_GS, however, at V_GS-V_T ≈ 2.3 V (untreated transistor) and V_GS-V_T ≈ 1.15 V (SDS-treated transistor), a decreasing µ_FET trend is observed, which can be attributed to the presence of charged defects present on the surface of cr-PVA. These charged defects in principle act as static charges forming energy valleys (negatively charged defects) and hills (positively charged defects) near to the I/S interface, since higher V_GS-V_T values correspond to lower l₀ (Figure 4b). At lower V_GS, the flow of charges is distributed more equally in the channel layer, to a great extent far from the I/S interface. Hence, there is limited interaction of charge carriers with the I/S interface charged defects, whereas, with increasing V_GS, the flow of charge carriers occurs very near to the interface in the channel bottleneck, being hindered by these charge defects originated electrostatic potential variations. The transistor in which the cr-PVA layer is treated with SDS exhibits flow of charge carriers at higher mobility values throughout the bottleneck (Figure 4b), which is attributed to a lower density of charged defects at I/S interface and the highest µ_FET value (1.05 cm² V^-1 s^-1) is observed at around l₀ = 9 nm.

Figure 4
Field effect charge carrier mobility as a function of: (a) V_GS-V_T, (b) minimum effective channel bottleneck thickness (l₀), for untreated and SDS treated transistors. In both cases V_DS = 5 V.

Sworakowski and co-workers used a mobility dependence on the distance z to the interface given by the function µ ∝ [1 - exp(-z/λ)] (where λ is a constant of the order of the molecular dimensions) to account for the interface neighborhood imposed mobility decay.^30,31 The variation in the average mobility with respect to l₀, when the effective channel bottleneck reaches its minimum thickness (|V_GS-V_T| → ∞) can then be described using:

(4) $\begin{array}{c}{\stackrel{─}{\mathit{\mu }}}_{\mathit{FET}}=\mathit{l}_0{}^{-1}{\int }_0^{{\mathit{l}}_0}\mathit{\mu }(\mathit{z})\mathit{dz}={\mathit{\mu }}_0\mathit{l}_0{}^{-1}{\int }_0^{{\mathit{l}}_0}[1-\exp (-\frac{\mathit{z}}{\mathit{\lambda }}\mathrm{)]}\mathit{dz}=\hfill \\ {\mathit{\mu }}_{}\{1-\frac{\mathit{\lambda }}{{\mathit{l}}_0}[1-\exp (-\frac{{\mathit{l}}_0}{\mathit{\lambda }}\mathrm{)]\}}\hfill \end{array}$

where µ₀ is the bulk mobility. It is important to keep in mind the limitations of this model, since around 30 nm, the effective channel thickness reaches full thickness of the C₆₀ layer near to the drain electrode (at low V_GS), hence the further decrease in mobility for larger l₀ is witnessed.

Previous reports on C₆₀-based OFETs have usually stressed on enhancing device performance by improving the metal contact/channel interface by reducing the contact resistance using several techniques.^32,33 Quite recently Du et al. demonstrated that µ_FET of C₆₀-based transistors can be improved by modifying the I/S interface properties. In their work they achieved a highest µ_FET of 0.31 cm² V^-1s^-1.³⁴ In top-contact FETs, there are typically two forms of resistances: metal contact/channel interface resistance and the organic channel resistance itself. Contact resistance can be reduced by tuning the injection barrier, whereas, for C₆₀-based OFETs very few studies are found dealing with the reduction of the channel resistance through the improvement of the transport in the vicinity of the I/S interface. Our work was aimed to minimize the effect of charged defects present on I/S interface and to enhance the properties of this region to obtain an overall enhanced OFET performance. After SDS treatment a better charge transport in the channel close to the I/S interface is observed, hence resulting in a ca.5-fold increase in µ_FET and g_m and additionally, a ca.8-fold increase in I_on/I_off.

4. Conclusions

In summary, this work was concerned with the development of C₆₀-fullerene based n-channel OFETs with cr-PVA gate dielectric. The performance of these devices was not found to be up to the mark when compared with previous reports on C₆₀-based OFETs. Hence in the quest of improving overall performance, a cost-effective but efficient method was applied, involving deposition of an additional layer of sodium dodecyl sulfate (SDS) anionic surfactant on top of the gate dielectric. The SDS acted as a treating agent, passivating the positively charged defects present on the surface of cr-PVA. Field-effect mobility µ_FET was analyzed as a function of channel bottleneck thickness and an increase in µ_FET was observed after SDS treatment. SDS acted as a part of cr-PVA, significantly improving the specific capacitance and crucial parameters including µ_FET, g_m and on/off current ratio.

5. Acknowledgements

The authors would like to thank CNPq and CAPES for research grants and fellowships.

References

• ¹
  Newman CR, Frisbie CD, da Silva Filho DA, Brédas JL, Ewbank PC, Mann KR. Introduction to Organic Thin Film Transistors and Design of n-Channel Organic Semiconductors. Chemistry of Materials 2004;16(23):4436-4451.
• ²
  Wöbkenberg PH, Bradley DDC, Kronholm D, Hummelen JC, de Leeuw DM, Cölle M, et al. High mobility n-channel organic field-effect transistors based on soluble C₆₀ and C₇₀ fullerene derivatives. Synthetic Metals 2008;158(11):468-472.
• ³
  Li H, Tee BCK, Cha JJ, Cui Y, Chung JW, Lee SY, et al. High-Mobility Field-Effect Transistors from Large-Area Solution-Grown Aligned C₆₀ Single Crystals. Journal of the American Chemical Society 2012;134(5):2760-2765.
• ⁴
  Kao CC, Lin P, Lee CC, Wang YK, Ho JC, Shen YY. High-performance bottom-contact devices based on an air-stable n-type organic semiconductor N, N-bis (4-trifluoromethoxybenzyl)-1,4,5,8-naphthalene-tetracarboxylic di-imide. Applied Physics Letters 2007;90(21):212101.
• ⁵
  Wang SD, Minari T, Miyadera T, Tsukagoshi K, Aoyagi Y. Contact-metal dependent current injection in pentacene thin-film transistors. Applied Physics Letters 2007;91(20):203508.
• ⁶
  Zhou J, Niu QL. Properties of C₆₀ thin film transistor based on polystyrene. Chinese Physics B 2010;19(7):077305.
• ⁷
  Anthopoulos TD, Singh B, Marjanovic N, Sariciftci NS, Ramil AM, Sitter H, et al. High performance n-channel organic field-effect transistors and ring oscillators based on C₆₀ fullerene films. Applied Physics Letters. 2006;89(21):213504.
• ⁸
  Cai X, Yu J, Zhou J, Yu X, Jiang Y. Mobility Improvement in C₆₀-Based Field-Effect Transistors Using LiF/Ag Source/Drain Electrodes. Japanese Journal of Applied Physics 2011;50(12R):124203.
• ⁹
  Zhang XH, Domercq B, Kippelen B. High-performance and electrically stable C₆₀ organic field-effect transistors. Applied Physics Letters 2007;91(9):092114.
• ¹⁰
  Itaka K, Yamashiro M, Yamaguchi J, Haemori M, Yaginuma S, Matsumoto Y, et al. High-Mobility C₆₀ Field-Effect Transistors Fabricated on Molecular- Wetting Controlled Substrates. Advanced Materials 2006;18(13):1713-1716.
• ¹¹
  Kitamura M, Kuzumoto Y, Kamura M, Aomori S, Arakawa Y. High-performance fullerene C₆₀ thin-film transistors operating at low voltages. Applied Physics Letters 2007;91(18):183514.
• ¹²
  Machado WS, Hümmelgen IA. Low-Voltage Poly(3-Hexylthiophene)/Poly(Vinyl Alcohol) Field-Effect Transistor and Inverter. IEEE Transactions on Electron Devices 2012;59(5):1529-1533.
• ¹³
  Machado WS, Hümmelgen IA. Low voltage organic field effect transistors with a poly(hexylthiophene)-ZnO nanoparticles composite as channel material. Physica Status Solidi (RRL) - Rapid Research Letters 2012;6(2):74-76.
• ¹⁴
  van Etten EA, Ximenes ES, Tarasconi LT, Garcia ITS, Forte MMC, Boudinov H. Insulating characteristics of polyvinyl alcohol for integrated electronics. Thin Solid Films 2014;568:111-116.
• ¹⁵
  Lee CA, Park DW, Jin SH, Park IH, Lee JD, Park BG. Hysteresis mechanism and reduction method in the bottom-contact pentacene thin-film transistors with cross-linked poly(vinyl alcohol) gate insulator. Applied Physics Letters 2006;88(25):252102.
• ¹⁶
  Hyung GW, Lee DH, Koo JR, Kim YK, Park J. Organic field-effect transistors with surface modification by using a PVK buffer layer on flexible substrates. Journal of the Korean Physical Society 2012;61(10):1720-1723.
• ¹⁷
  Cruz-Cruz I, Tavares ACB, Reyes-Reyes M, López-Sandoval R, Hümmelgen IA. Interfacial insertion of a poly (3, 4-ethylenedioxythiophene): poly (styrenesulfonate) layer between the poly (3-hexyl thiophene) semiconductor and cross-linked poly (vinyl alcohol) insulator layer in organic field-effect transistors. Journal of Physics D: Applied Physics 2014;47(7):075102.
• ¹⁸
  Nawaz A, Cruz-Cruz I, Rodrigues R, Hümmelgen IA. Performance enhancement of poly (3-hexylthiophene-2, 5-diyl) based field effect transistors through surfactant treatment of the poly (vinyl alcohol) gate insulator surface. Physical Chemistry Chemical Physics 2015;17(40):26530-26534.
• ¹⁹
  de Col C, Nawaz A, Cruz-Cruz I, Kumar A, Kumar A, Hümmelgen IA. Poly(vinyl alcohol) gate dielectric surface treatment with vitamin C for poly(3-hexylthiophene-2,5-diyl) based field effect transistors performance Improvement. Organic Electronics 2015;17:22-27.
• ²⁰
  Jastrombek D, Tavares ACB, Meruvia MS, Koehler M, Hümmelgen IA. Improved charge carrier mobility in copper phthalocyanine based field effect transistors by insertion of a thin poorly conducting layer as gate insulator extension. Physica Status Solidi (A) 2015;212(12):2759-2765.
• ²¹
  Jastrombek D, Nawaz A, Koehler M, Meruvia MS, Hümmelgen IA. Modification of the charge transport properties of the copper phthalocyanine/poly(vinyl alcohol) interface using cationic or anionic surfactant for field-effect transistor performance enhancement. Journal of Physics D: Applied Physics 2015;48(33):335104.
• ²²
  Toniolo R, Hümmelgen IA. Simple and Fast Organic Device Encapsulation Using Polyisobutene. Macromolecular Materials and Engineering 2004;289(4):311-314.
• ²³
  Seidel KF, Koehler M. Modified Lampert triangle in an organic field effect transistor with traps. Physical Review B 2008;78(23):235308.
• ²⁴
  Matsuoka Y, Inami N, Shikoh E, Fujiwara A. Transport properties of C₆₀ thin film FETs with a channel of several-hundred nanometers. Science and Technology of Advanced Materials 2005;6(5):427-430.
• ²⁵
  Hamed A, Sun YY, Tao YK, Meng RL, Hor PH. Effects of oxygen and illumination on the in situ conductivity of C₆₀ thin films. Physical Review B. 1993;47(16):10873.
• ²⁶
  Pevzner B, Hebard AF, Dresselhaus MS. Role of molecular oxygen and other impurities in the electrical transportand dielectric properties of C₆₀ films. Physical Review B 1997;55(24):16439.
• ²⁷
  Könenkamp R, Priebe G, Pietzak B. Carrier mobilities and influence of oxygen in C₆₀ films. Physical Review B 1999;60(16):11804.
• ²⁸
  Benvenho ARV, Machado WS, Cruz-Cruz I, Hümmelgen IA. Study of poly(3-hexylthiophene)/cross-linked poly(vinyl alcohol) as semiconductor/insulator for application in low voltage organic field effect transistors. Journal of Applied Physics 2013;113(21):214509.
• ²⁹
  Shea PB, Kanicki J, Ono N. Field-effect mobility of polycrystalline tetrabenzoporphyrin thin-film transistors. Journal of Applied Physics 2005;98(1):014503.
• ³⁰
  Sworakowski J, Bielecka U, Lutsyk P, Janus K. Effect of spatial inhomogeneity of charge carrier mobility on current-voltage characteristics in organic field-effect transistors. Thin Solid Films 2014;571(Part 1):56-61.
• ³¹
  Sworakowski J. Current-voltage characteristics in organic field-effect transistors. Effect of interface dipoles. Chemical Physics 2015;456:106-110.
• ³²
  Kubozono Y, Haas S, Kalb WL, Joris P, Meng F, Fujiwara A, et al. High-performance C₆₀ thin-film field-effect transistors with parylene gate insulator. Applied Physics Letters 2008;93(3):033316.
• ³³
  Zhang XH, Kippelen B. High-performance C₆₀ n-channel organic field-effect transistors through optimization of interfaces Journal of Applied Physics 2008;104(10):104504.
• ³⁴
  Du L, Luo X, Wen Z, Zhang J, Sun L, Lv W, et al. A striking performance improvement of fullerene n-channel field-effect transistors via synergistic interfacial modifications. Journal of Physics D: Applied Physics 2015;48(40):405105-405114.

Publication Dates

• Publication in this collection
  19 Sept 2016
• Date of issue
  Sep-Oct 2016

History

• Received
  07 Dec 2015
• Reviewed
  07 June 2016
• Accepted
  20 Aug 2016