A line-interactive UPS system implementation with series-parallel active power-line conditioning for three-phase, four-wire systems

ELETRÔNICA DE POTÊNCIA

A line-interactive UPS system implementation with series-parallel active power-line conditioning for three-phase, four-wire systems

Sérgio Augusto Oliveira da Silva^I; Pedro F. Donoso-Garcia^II; Porfírio C. Cortizo^II; Paulo F. Seixas^II

^IDepartamento de Engenharia Elétrica – CEFET-PR, Av. Alberto Carazzai, 1640 - Centro. CEP. 86.300-000 – Cornélio Procópio-PR, Brasil. [e-mail]

^IIDepartamento de Engenharia Eletrônica – UFMG, Av. Antônio Carlos, 6627 - Pampulha. CEP. 31.270-901 – Belo Horizonte-MG, Brasil. [e-mail]; [e-mail]; [e-mail]

ABSTRACT

This paper presents a three-phase line-interactive uninterruptible power supply (UPS) system with active series-parallel power-line conditioning capabilities. Synchronous reference frame (SRF)-based controller is used for harmonic and reactive power compensation generated from any configuration of non-linear loads. Under normal line conditions the UPS system works with universal filtering capabilities, such as compensating the input currents and output voltages. Two three-phase pulsewidth modulation (PWM) converters, called series and parallel active filters, are used to perform the series and parallel active power-line compensation. The series active filter works as sinusoidal current source in phase with the input voltage, drawing from utility sinusoidal and balanced input currents with low total harmonic distortion (THD). The parallel active filter works as sinusoidal voltage source in phase with the input voltage, providing regulated and sinusoidal output voltages with low THD. The performance of the UPS system is evaluated in three-phase, four-wire systems. Experimental results are presented to confirm the theoretical studies.

Keywords: Active Filter; UPS; Harmonics.

RESUMO

Este artigo apresenta um sistema de energia ininterrupta (SEI) line-interactive trifásico com capacidade de condicionamento ativo de potência série e paralelo. Um controlador baseado no sistema de eixo de referência síncrona (SRF) é usado na compensação de potência reativa e harmônica geradas por quaisquer configurações de cargas não lineares. Sob condições normais da rede elétrica o SEI trabalha na compensação das correntes de entrada e das tensões de saída. Dois conversores controlados em tensão e modulados por largura de pulso (PWM), chamados de filtros ativos série e paralelo, são usados para realizar o condicionamento ativo de potência série e paralelo. O filtro ativo série trabalha como uma fonte de corrente senoidal em fase com a tensão de entrada, drenando da rede correntes senoidais, balanceadas com baixas taxas de distorção harmônica (TDH). O filtro ativo paralelo trabalha como uma fonte de tensão senoidal em fase com a tensão de entrada, fornecendo para a carga tensões reguladas, senoidais e com baixas taxas de distorção harmônica. O desempenho do SEI é avaliado para sistemas trifásicos com quatro fios. Resultados experimentais são apresentados para confirmar os estudos teóricos.

Palavras chaves: Filtro ativo, SEI, Harmônicas.

1 INTRODUCTION

The large use of non-linear loads, such as, personal computers, UPS, etc., has increased in the last years, causing problems to the power supply systems. The harmonic currents drawn by non-linear loads from utility have contributed to reduce the power factor and to increase the total harmonic distortion (THD) in the utility input voltages. The problem increases when single-phase non-linear loads are connected in three-phase, four-wire systems. In this case, as the phase currents are not sinusoidal, even perfectly balanced single-phase loads can result in significant neutral currents and their amplitude can exceed the amplitude of the line currents (Gruzs, 1990). If the non-linear loads are unbalanced, the input currents will be unbalanced in terms of fundamental and harmonic components, and a very large third component and its multiples will flow in the neutral wire. The excessive neutral currents can cause damage both in the neutral conductor and in the transformer to which it is connected (Quinn et al., 1992). Thereby, active filter topologies have been used to compensate neutral harmonic currents (Quinn et al., 1992; Quinn et al., 1993; Thomas el al., 1996).

Uninterruptible power supply (UPS) systems have enabled the improvement of power source quality, providing clean and uninterruptible power to critical loads such as industrial process controls, computers, medical equipment, data communication systems, and protection against power supply disturbances or interruptions (Oliveira da Silva et al., 2001; Kamran et al., 1995; Jeon et al., 1997, Cheung et al., 1996; Lin et al., 1993). In (Lin et al., 1993) a three-phase parallel processing UPS has been presented with harmonic and reactive power compensation, but the output voltages and the input currents cannot be controlled simultaneously. Three-phase UPS systems with series-parallel active power-line conditioning have been proposed using different control strategies (Oliveira da Silva et al., 2001; Kamran et al., 1995). In (Kamran et al., 1995) the three-phase UPS system was employed for three-wire systems, and in (Oliveira da Silva et al., 2001), albeit it can be employed for three-wire and four-wire systems, the UPS was used to feed a non-linear load composed by a three-phase non-controlled rectifier, in which neutral currents do not exist.

This paper presents a three-phase line-interactive UPS system with active series-parallel power-line conditioning capabilities using an SRF-based controller, for three-wire and four-wire systems in which three single-phase loads are fed. In UPS standby operation mode, the series active power filter acts as a sinusoidal current source and the parallel active power filter acts as a sinusoidal voltage source (Oliveira da Silva et al., 2001). The output voltages are controlled to have constant rms values and low THD and the source currents are controlled to be sinusoidal and balanced with low THD. Both input currents and output voltages are simultaneously controlled to be in phase with respect the input voltages. Therefore, an effective power factor correction is carried out.

The control algorithm using SRF method and the active power flow through the UPS system are described and analytically studied. Design procedures, digital simulations and experimental results for a prototype are presented in order to verify the good performance of the proposed three-phase line-interactive UPS system.

2 DESCRIPTION OF THE LINE-INTERACTIVE UPS TOPOLOGY

The topology of the line-interactive UPS system is shown in Fig. 1. Two pulsewidth modulation (PWM) converters, coupled to a common dc-bus, are used to perform the series active filter and the parallel active filter functions. Capacitors and a battery bank are placed in the dc-bus and a static switch ‘sw’ is used to provide the disconnection between the UPS system and the power supply when an occasional interruption of the incoming power occurs. The center-tap of the dc-bus is connected to the utility neutral.

3 SYNCHRONOUS REFERENCE FRAME AND STATE FEEDBACK CONTROLLERS

3.1 Current SRF-Based Controller (Standby Mode)

An SRF-based controller is used to provide and to control the compensating reference currents (, , and ) for the series PWM converter shown in Fig. 1. The block diagram of the control scheme for current compensation is shown in Fig. 2. The three-phase load currents (i_La, i_Lb, i_Lc) are measured and transformed into a two-phase stationary reference frame (dq)^s quantities (id^s, iq^s) based on the transformation (1). Then, these quantities are transformed from a two-phase stationary reference frame (dq)^s into a two-phase synchronous rotating (dq)^e reference frame, based on the transformation (2), where q = wt, is the angular position of the reference frame. The unit vectors sinq and cosq are obtained from PLL system. The currents at the fundamental frequency w (id^e and iq^e) are now dc values and all the harmonics, transformed into non-dc quantities, can be filtered using a low pass filter (LPF) as shown in Fig. 2. Now, represents the fundamental active component of the load current and represents the fundamental reactive component of the load current, both in dq axis.

An additional dc-bus controller is responsible for regulating the current I_dc and the voltage V_dc . Apart from the conventional active filter applications, in which only the dc-bus voltage is controlled, the UPS dc-bus controller is able to control the dc-bus current for adequate charging of the battery bank. The dc-bus controller is also responsible to control the active power flow of the UPS system. Its output ib_dc is added to the active current in the d axis as given by (3) and, thus, the amplitude of the reference currents can be controlled by .

Now, the dc components of the synchronous reference frame and can be transformed into the stationary reference frame (dq)^s. The inverse transformation matrix from two-phase synchronous reference frame to two-phase stationary reference frame is given by (4). As only the fundamental active component reference needs to be obtained, (4) can be replaced by (5).

The matrix that provides the linear transformation from two-phase system to three-phase stationary reference frame system is given by (6). Thereby, the dc component of the synchronous reference frame is transformed into the stationary reference frame (dq)^s and yields the fundamental components of the load currents (, , and ). Such reference currents are generated in software.

3.2 State Feedback Current Controller (Standby Mode)

The single-phase block diagram of the current controller is shown in Fig. 3. The load currents (i_La,b,c) are measured and from the current SRF controller the sinusoidal current references () are obtained. From Fig. 3, the closed-loop transfer function i_c(s)/(s) is found as (7), in which the gain of the PWM block is one.

The dynamic stiffness transfer function of the series converter is given by (8), which is defined as the magnitude of the difference between the input and output voltages that causes a unit deviation in input current i_s (i_c): |(n_f(s) – n_s(s))/i_c(s)|. The voltage difference is considered as a disturbance.

The frequency response of equation (7) is shown in Fig. 4 (a) and ^(b). At the power system frequency (w = 377 rad/s), the gain of the system transfer function is about 0 dB and the phase shift is nearly zero degree. The bandwidth of the system is about 1600 Hz. Fig. 5 shows the dynamic stiffness frequency response of the current controller. It can be noted high impedance obtained from (8) in a large range of the frequency spectrum, which is enough to isolate the line from the load with respect to current harmonics. The parameters and gains used to plot the curves of Figs. 4 and 5 are listed in Table 1.

3.3 State Feedback Voltage Controller (Standby and Backup Modes)

The parallel converter controls the output voltages to be in phase with the input voltages. Besides, the output voltages should be constant rms values with low THD. Similar to the control algorithm for input current compensation, the reference voltages () are generated by software using a PLL system (Oliveira da Silva et al., 2001).

Fig. 6 shows the single-phase block diagram of the voltage controller, with an outer voltage loop and an inner current loop. To anticipate any errors to occur in the output voltage, a disturbance input decoupling is implemented by measuring the load current i_L and the source current i_s. The difference between them is used as an additional current loop command. Thus, only the capacitor current is used as a feedforward command (). To simplify the control, such command was used only to plot the curves of Figs. 7 and 8 but it was not implemented in laboratory. From Fig. 6, the closed-loop transfer function n_f(s)/(s) is found as (9), in which the gain of the PWM block is one.

The dynamic stiffness transfer function of the parallel converter is given by (10), which is defined as the magnitude of the difference between the output and input currents that causes a unit deviation in output voltage n_f: |(i_L(s) – i _s(s))/n_f(s)|. The current difference is considered as a disturbance.

The coefficients X_n and Y_n of the equation (9) and (10) are given by (11).

The frequency response of equation (9) is shown in Fig. 7 (a) and (b). At the power system frequency (w = 377 rad/s), the gain of the system transfer function is about 0 dB and the phase shift is nearly zero degree. The bandwidth of the system is about 6000 Hz. Fig. 8 shows the dynamic stiffness frequency response of the voltage controller. It can be seen a high admittance obtained from (10) in a large range of the frequency spectrum, which is enough to absorb the harmonic currents of the load.

The parameters and gains used to plot the curves of Figs. 7 and 8 are listed in Table 2.

3.4 Relation between the series |Z_s| and the parallel |Z_p| Impedances.

From Fig. 8, it can be noted that the higher impedance of the parallel converter occurs at 3 KHz (|Z_pmax| = 0,4W). At this same frequency, from Fig. 5, the impedance of the series converter is |Z_s| = 20W. Thus, the relation between |Z_s| and |Z_pmax| is approximately 50. This is enough for the parallel converter to absorb the harmonic currents of the load.

From Fig. 5 it can be seen that the lower series impedance occurs at 1,15 KHz (|Z_smin| = 12W). At this same frequency, from Fig. 8, the impedance of the parallel converter is |Z_p| = 0,05W. Thus, the relation between |Z_smin| and |Z_p| is approximately 240. This is enough for the series converter to isolate the line from the load with respect to current harmonics of the load.

4 ACTIVE POWER FLOW THROUGH THE UPS SYSTEM

The direction of the active power flow through the UPS system is shown in Fig. 9. It can ever change because the amplitude of the input voltages is variable.

Both the apparent powers S_s and S_p, handled by the series and by the parallel converters, respectively, depend on the ratio between the output and input rms voltages (V_f/V_s), the displacement factor (cos f₁) and the THD of the load current i_L (THD_iL). In steady state, assuming a balanced sinusoidal system, the normalized powers handled by the parallel converter |S_p/S_L| and by the series converter |S_s/S_L| are given by equations (12) and (13), respectively. The quantities S_L, P_L, Q_L and H_L are the apparent, active, reactive and harmonic powers of the load, respectively.

In Fig. 10 (a) and ^(b) the normalized powers handled by the parallel converter |S_p/S_L| and by the series converter |S_s/S_L| are plotted for two different displacement factors (cos f₁= 1.0 and cos f₁= 0.7). These curves can be used to determine the power rate of the series and the parallel PWM converters.

If the charging of the batteries is taking into account, additional active power P_b, given by (14), should be included in the analysis.

Thus, equations (16) and (17) replace equations (12) and (13), respectively, where the charging factor k_b is ever greater than zero, and P, given by equation (15), is the sum of active load power P_L and active power P_b, used to charge the battery bank.

The plots of the normalized powers for two different values of k_b (k_b = 0 and k_b= 0.1) are shown in Fig. 11 (a) and ^(b).

To fixed displacement factor (cos f₁) and load current THD, depending on the k_b value and the input voltage deviation from the desired output voltage, the batteries charging can be realized either from the series or parallel converters or from both as can be observed in Fig. 11 (a).

5 EXPERIMENTAL RESULTS

The complete scheme of the three-phase line-interactive UPS system is shown in Fig. 12. To verify the performance of the three-phase line-interactive UPS system, a prototype was developed and tested. Three single-phase non-linear loads with high load current THD are used to test the line interactive UPS system. The parameters used in the prototype are: L_fp= 300µH, L_fs= 1.4mH, C_fp= 130µF, R_La= 62 W, R_Lb= 55 W, R_Lc= 70W, C_La,b,c= 470µF, nominal rms line-to-neutral input voltages - V_sa,b,c= 120V, nominal rms line-to-neutral output voltages - V_fa,b,c= 115V and dc-bus voltage - V_dc= 570V. The apparent power rates of the unbalance loads are: S_a= 560 VA, S_b= 630 VA, and S_c= 540 VA.

The part of the scheme shown in the shaded area uses a 400MHz PC computer, a 12 bits resolution data acquisition system and a 12 bits resolution D/A converter board. Both current SRF controller and PLL system (Fig. 2) are implemented in software and are responsible to generate the current and voltage references for the current and voltage analog controllers. Both data acquisition systems and digital controllers run at 5kHz frequency.

The output voltages (n_fa,b,c) and load currents (i_La,b,c) are shown in Fig. 13 (a), (b) and (c). Despite of the load current THD to be approximately 100% the THD of the regulated and balanced output voltages is less than 4%.

Fig. 14 (a) shows the three-phase source voltages V_sa,b,c and Fig. 14 (b) shows the source currents i_sa,b,c. The parallel compensation currents () are shown in Fig. 14 (c). It can be noted that the source currents are almost sinusoidal and balanced and their THD_iL are approximately 10%.

Details of the source currents, parallel compensation currents and uncompensated currents, for phases a, b and c, are shown in Fig. 15 (a), (b), and (c), respectively. Fig. 16 shows output voltage and input current of the phase a. Both input currents and output voltages are in phase with the input voltages. The measured power factor (cos j) is equal to 0,982.

The neutral conductor load current and the neutral conductor utility current are shown in Fig. 17 (a) and (b), respectively. It is observed from Fig. 17 (b) that the amplitude of the utility neutral current has been reduced considerably.

The input voltage (n_sa), the output voltage (n_fa) and the difference between them (n_ca) are shown in Fig. 18 (a), which shows that the output voltages are in phase with respect the input voltages. For the load currents shown in Fig. 13 and the ratio between the output and input rms voltages (V_f/V_s) presented in Fig. 18 (a), the source reference currents obtained from the SRF-based controller of Fig. 2, can be seen in Fig. 18 (b).

The quantities n_fa, i_sa, i_La and (reference input current) are shown in Fig. 19 (a), for standby to backup transition mode that occurs at 0.02s. When the input power is out the input switch 'sw' is opened and the input current i_sa drops to zero, but the output voltage n_fa remains providing power to the load. Thus, the PLL system forces the UPS to operate at a fixed reference frequency (w*= 377 rad/s).

The transition from backup to standby operation mode of the UPS system occurs at 0.31s, as shown in Fig. 19 (b) and (c). When the input power returns, the PLL system synchronizes the UPS system with respect the utility and the switch 'sw' is closed. Thereby, immediately the input current i_sa follows the reference .

Note that the output voltage is unaffected by the transitions from standby to backup mode and from backup to standby mode. Fig. 19 (d) shows the UPS operating in standby mode.

Both Figs. 18 and 19 were obtained from data acquisition software.

6 CONCLUSIONS

A three-phase line-interactive UPS system topology with active series-parallel power-line conditioning capabilities has been implemented and tested for four-wire systems. With SRF-based controller implementation, balanced and almost sinusoidal input currents with low THD were obtained. The levels of both fundamental and harmonic contents of the utility neutral current have been reduced considerably. The output voltages are balanced and almost sinusoidal with low THD.

The main advantage of the presented line-interactive UPS topology, when compared to the on-line topology, which uses two cascaded PWM power converters working at full power rating, is the smaller power rating handled by both series and parallel converters during the standby mode, increasing the efficiency of the UPS. The high series impedance and the low parallel impedance can protect the load against mains transients.

It has been demonstrated that the experimentally obtained results agree with good approximation with the theoretically predicted results.

Recebido em 30/10/02

1ªrevisão em 20/12/02

2ªrevisão em 18/02/03

3ªrevisão em 24/03/03

Aceito s/recom.do Ed.Ass. Prof. José Antenor Pomilio

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Publication Dates

• Publication in this collection
  14 Oct 2005
• Date of issue
  June 2005

History

• Reviewed
  24 Mar 2003
• Received
  30 Oct 2002