Effective limitation of line fault currents by means of the series-connected VSC-based facts devices

SISTEMAS DE POTÊNCIA

Effective limitation of line fault currents by means of the series-connected VSC-based facts devices

R.L. Vasquez-Arnez^I; L.C. Zanetta Jr.^I; F.A. Moreira^II

^IDepartment of Electrical Engineering, University of São Paulo, CEP 05508-900, SP

^IIDepartment of Electrical Engineering, Federal University of Bahia, CEP 40210-630, BA

ABSTRACT

In this paper, the nearly instantaneous response of the series-connected VSC-based FACTS controllers when used to limit possible fault currents in a compensated line, will be presented. The effectiveness of both FACTS controllers (SSSC and UPFC) towards this system condition was investigated exploring the series voltage effect upon the line. Moreover, it will be shown that the UPFC shunt converter can also contribute to the reduction of such fault currents. The short-circuit current limitation strategy presented herein showed that aside of the power flow control and voltage support commonly carried out by the SSSC and the UPFC, they could also perform this additional functionality, thus offering a useful tool for the protection of the line in which these devices are installed.

Keywords: FACTS, Short-circuit, SSSC, UPFC, VSC.

1 INTRODUCTION

Short-circuit current limiters could be implemented because of two reasons: to reduce the stress within the network and/or to limit the stress over a certain asset, as it might be the case of the series-connected converters referred in this paper. Modern power systems are built with a high degree of flexibility so that, ideally, a minimum part of the system would be interrupted during the fault period. Presently, investigations are being carried out to study the coordination of the distance protection and the line's apparent impedance variation of those lines implemented with FACTS (Flexible AC Transmission Systems) devices, mainly those connected in series with the line. Also, the fault clearing time is not instantaneous for it depends on the operating time imposed to the overcurrent relays and the circuit-breaker's tripping time.

The series-connected VSC (Voltage-Sourced Inverter) based FACTS devices referred in this paper, are: the SSSC (Static Synchronous Series Compensator) and the UPFC (Unified Power Flow Controller). These devices have nearly instantaneous responses and enable to control more effectively the power flow on the lines where they are installed. As it is known, both the SSSC and the UPFC basically inject a nearly sinusoidal voltage (V_se) in series with the line. The voltage (V_q) of the former is in quadrature at an angle ±90º with respect to the line current. The latter also injects a series voltage to the line, but its phase angle can freely rotate along the 360 degrees describing a circle whose maximum radius is equal to .

Both VSC-based compensators use a DC capacitor as a source for the waveform generation. The presence of transients in the compensated line (short-circuits, etc) causes the DC voltage in both devices to fluctuate. This fluctuation is proportional to the line current and to the injected voltage itself. The UPFC shunt VSC helps to cope with this problem by controlling the DC voltage. In other words, the shunt converter damps these fluctuations and keeps the DC voltage almost constant. In this work, it will be considered that the referred fluctuations do not alter significantly the compensation characteristic of the devices aimed to limit the fault currents.

In recent years, some other FACTS devices have emerged for developing similar functions. It is the case of the SCCL (Short Circuit Current Limiter) which has shown to be effective for this specific purpose; it is also the case of the TCSC (Thyristor Controlled Series Capacitor) as reported by Moschakis et alii (2003). The fault limitation approach presented here may not be cheaper nor simpler than other type of short-circuit current limitation strategies, but it does explore this attractive tool and additional functionality of the series-connected VSC-based FACTS controllers.

In this article, it will be presented the basis to manipulate the series voltage injected from both the SSSC and the UPFC, so as to get the maximum effect whilst limiting short-circuit currents. Further, it will be shown that the UPFC shunt converter can also contribute to the reduction of fault currents by forcing the bus voltage at its point of connection, therefore at the fault point, to reduce its magnitude.

2 FAULT CURRENT LIMITATION

It is well established that the short-circuit current levels in a certain network increases proportionally with the addition of lines and new generation. This may jeopardize the transformation and transmission assets in existing power systems, for the short-circuit current rating of such equipment, if not modified and updated or even replaced, will be exceeded. Under these circumstances, the fault current limitation offered by modern controllers, characterized by their nearly instantaneous responses, may become crucial in diminishing such large currents. Hence the interest for analyzing the topic discussed in this paper.

The fault current limitation based on impedance control is a well known subject. For three-phase faults, the inclusion of limiting reactors is a common method whereas for phase-to-ground faults, the use of grounding devices and modifications of the zero sequence impedance, are usual practices. However, information on the use and application of the FACTS devices for short-circuit limitation is somewhat scarce. In a study presented by Salem and Sood (2005) a PWM (Pulse Width Modulation) VSC-based SSSC built in the EMTP RV program, is presented. Although in that paper it is also addressed the fault current limitation as an outstanding byproduct of this device, the authors mainly emphasized aspects such as the inverter's waveform generation technique and the control system of both the converter itself and the quadrature voltage injected onto the line. The scope of our paper, unlike the one mentioned, emphasizes the effect and contribution of the FACTS devices herein referred for limiting fault currents. Still, whenever applicable details of either device implemented in the ATP program, will be included.

The respective leakage reactance of the series coupling transformer reduces, although to a smaller extent, the short-circuit current that may be originated in the compensated line (passive fault limitation). Thus, if an emulated reactance of greater value is inserted into the line, in an almost instantaneous way, the stress of the compensated line as a result of the fault, can be limited to a considerable degree.

The fault limitation strategy using FACTS devices was first explored by Duangkamol et alii (2000) followed by Takeshita et alii (2002). Here, we will further explore this topic and will show the contribution of the UPFC shunt and series converters towards this system condition. The system depicted in Figure 1, will be used to analyze and simulate the referred fault current limitation strategy. The simple connection of the switch, SW1, makes of the stand-alone operating VSCs (SSSC and STATCOM) to complete the UPFC arrangement. Typically, both SSSC and UPFC devices are mainly used for power flow control (Gyugyi, 1991; Papic et alii, 1997; Huang et alii, 2000; Vasquez-Arnez et alii, 2002 and Sen, 1998). An additional function of the shunt VSC being the line voltage support.

Under no fault conditions, the voltage (V_se) and its respective angle (q_se), will give rise to a family of curves like those depicted in Figure 2. To obtain these curves both series and shunt converters were regarded as ideal sources operating at fundamental frequency (Uzunovic et alii, 1998; Yu et alii, 1996). Also, the resistive component in each transmission line was neglected and both sending and receiving-end ideal sources were set to 1.0 pu at angles 0º and -30º, respectively. The referred steady-state curves show the extent in which the line's active and reactive power in the receiving-end, can be controlled. Notice, for the forthcoming analysis, the values of the series angle (q_se) for which P and Q are substantially compensated.

The condition to achieve the short-circuit current limitation is to keep the voltage V_se (V_q in the SSSC configuration) injected in the line even during the fault period. Recall that for the SSSC case (Sen, 1998), the relation of the quadrature series voltage, V_q, over the line current will be seen by the system as a compensating reactance, X_C, which emulates an inductive (or capacitive) reactance in series with the line V_q / I_L = ±jX_C. As for the UPFC, the relation between the series voltage, V_se, and the line current can be seen as a positive (negative) resistance (±R) and a positive (negative) reactance (±jX) in series with the line (Gyugyi, 1991). Although this concept can be used to explain the fault current limiting effect, we will prefer to analyze such current control from the series injected voltage viewpoint.

The idea behind the fault-current limitation concept (for three-phase and phase-to-ground faults) is to minimize the voltage at the fault point through the action of the series voltage, V_se. This, in fact, is an extension of the Thevenin's pre-fault voltage concept at the fault point. For the case of a three-phase fault occurring at bus 3 (Figure 3), it can be seen the contributions of the two independent loops L (left) and R (right) to the fault point. In fact, the series voltage will reduce the current contribution from the left AC system (E₁).

This reduction will be more effective when the UPFC injects positive sequence voltages in opposition to the left equivalent source, which can be estimated in each operative condition. If it is intended to minimize the total current at the fault point, the series voltage injected must be in opposition to the pre-fault voltage at the fault point. As the voltage along the line has a smooth behavior, it is not difficult to set values to cover some other cases of faults along the compensated line.

3 FAULT CURRENT LIMITATION ANALYSIS

Initially, it will be defined the left and right equivalent impedances, from the fault point up to each AC source, as Z_L and Z_R, respectively. For a phase-to-ground fault, which is the case more likely to occur, the sequence diagrams are sequentially connected, therefore, to minimize the current contributions to the fault, a more careful analysis must be performed. Such an analysis can be done through phase or sequence components.

Thus, regarding the fault point considered in Figure 3, which can be located at any point along the line Z₂, and with the term X_se included within the equivalent impedance Z_L (left-side), it can be established that:

Under the absence of the fault, the line current in the system will be,

The pre-fault voltage at bus 3 can be expressed as:

Substituting (2) into (3) and calling M the matrix that represents the voltage divider, yields:

where, [I] represents the identity matrix. Also,

In order to simplify (4), the first two terms (i.e. those affected by E₁, E₂ without the effect of V_se) will be named as V_uf (uncompensated fault voltage), whereas the last term will be designated as V_sc (series compensating voltage at the fault point F). Thus, the compensated fault voltage (V_f) in (4), former V₃, becomes:

To minimize V_f, the compensation term [M][V_se] has to be in opposition to V_uf, with the series voltage (V_se) being inserted at its maximum possible magnitude during the fault period.

The above equations and analysis correspond to a generic case of a tripolar fault. For the case of a phase-to-ground fault, some other aspects, such as the effect of the healthy phases should also be considered. This aspect is to be clarified (i.e. to observe whether the coupling effect of the unaffected phases can contribute or not to the fault current limitation). In the analyzed case only the inductive effect of the unaffected phases, will be considered. So, if the product of the resulting impedance matrices in (5) were renamed as that shown in () where to simplify the analysis transposed lines are considered, we will have:

Factors a, b are dependent on the equivalent impedances Z_L and Z_R and on the zero and positive sequence values which define the coupling effect between phases. The substitution of (7) into (6), yields:

For instance, the corresponding terms affecting the fault point at phase a, are:

For the case of the system depicted in Figure 3, if Z_L1=0.25, Z_L0=0.545, Z_R1=0.25, Z_R0=0.8695, then, the values of the factors a and b computed, will be: a=0.538 and b=0.038. Thus, according to (9) two different strategies can be adopted for analyzing the effect of the voltage V_se.

a) Regarding the positive sequence in the three phases , then, the voltage V_se at phase a will be:

in this case, the healthy phases can introduce a deleterious effect on the voltage at the fault point.

b) With the introduction of the zero sequence voltage equation (9) becomes:

The voltage control is improved compared to the previous positive sequence voltage compensation.

In order to analyze the contribution of the currents to the fault point, it will also be examined the sequence impedance diagrams depicted in Figure 4, in which:

: sequence components of the fault current.

: sequence components of the left-side equivalent contribution.

The loop equations from the diagram shown in Figure 4 are:

or, in its compact form:

Voltages and are the sequence components of the series voltage injected by the UPFC. Recalling also that:

Where: [Y] = [Z]^–1, then the zero sequence fault current can be obtained through (15):

The first two terms of the second member in (15) represent the fault current without the presence of the series voltages. The remaining terms representing the contribution of the series voltage. Obviously, the fault current can be obtained through:

Equation (14), shown some lines above, is in accordance to the concept of minimizing the pre-fault voltage at the fault point and it shows the most significant effect of applying positive or zero sequence voltage by analyzing the admittance matrix terms with positions Y₄₁ or Y₄₃, similarly to the analysis developed in (10) and (11). Let's now obtain the left-side equivalent contribution to the fault current.

This current is obtained through the addition of the first three rows in (14) in which the equivalent admittances are defined as:

where, Y_j is composed by the sum of the first three elements of each column.

A similar expression to that shown in (14) can be developed for the left-side current contribution (I_LC) to the fault current. That is:

Again, the first two terms of the second member in (19) refers to the fault current contribution without the series voltage (), whereas the remaining terms refer to the series voltage contribution (). In order to minimize the contribution to the total fault current, must be in opposition to . The best strategy for applying either the positive or zero sequence voltage from , for each specific system, must be chosen analyzing the elements Y₁ and Y₃ defined in (18). For example, using the parameters previously given, it can be obtained the respective Y matrix:

For this case, Y₁=-j0.1135 pu and Y₃=-j0.1554 pu, thus, the values computed for the currents in (19) result in: =15.46Ð-95.56ºpu, =5.25Ð87ºpu, =10.22Ð-96.87º pu. For this particular system, the zero sequence application of the series voltage, , becomes more effective to reduce the left equivalent contribution to the fault current. Finally, with the sequence components it can also be analyzed the total fault current in (15). As |Y₄₃| > |Y₄₁|, the zero sequence voltage is again more effective for the total fault current reduction, this being in agreement with our previous analysis performed with phase components.

3.1 UPFC MODEL AND IMPLEMENTATION

In this section, it will be presented the main aspects related to the UPFC implementation in the ATP program. In order to generate the waveforms in each VSC, it was used the Harmonic Neutralized (HN) technique which consists in the series connection of all the wye connected secondary windings of the transformers within the magnetic circuit. In this way, the equivalent output waveform, containing 12, 24 or 48 pulses, will be composed by the sum of all the individual 2-level or 3-level inverters, depending on the type of configuration used. So as to generate the desired waveforms, the phase-shift among the inverters implemented must be properly set up. The four VSC-based inverters depicted in Figure 5, upon which was built our model, make use of this technique using common D-Y transformers as the magnetic interface between the VSCs and the AC system. A more detailed description on the waveform generation using this technique can be found in the reference authored by Sen et alii (1998).

The control sequence followed by the UPFC shunt current (I_sh) and the series voltage (V_se) along with their associate variables, are shown in Figures 6(a) and 6(b), respectively. The shunt controller adjusts dynamically the phase angle between the VSC-1 and bus V₂ in order to generate or absorb MVArs at the connection point. The series VSC operates similarly to the shunt controller, in this case though adjusting the series angle. The variables with a superscript ref can be specified and will become the reference values for the controllers' adjustment. The errors between the measured and the specified values in each VSC are processed in a PI controller that computes the respective output variables.

On the other hand, the main parameters considered in the implementation of the UPFC, were (table 1):

The results corresponding to the steady-state operation of the UPFC, are shown in Fig. 7. Notice the output waveform of the shunt inverter (V_sh) depicted in Fig. 7(a) and the effect of the series voltage (V_se) over the power flow (Fig. 7b). The steady-state operation of the SSSC implemented, also showed satisfactory results. The SSSC implementation and waveform generation in ATP virtually followed the same procedure as its akin UPFC, except for the aforementioned quadrature operation of its series voltage imposed.

4 SIMULATION RESULTS

In this section, it will be shown the simulation results obtained in the ATP program. The system depicted in Figure 1, was used to simulate and assess the SSSC and the UPFC effectiveness in limiting the fault currents. For all the simulated cases (except Figure 10), the ground switch was set to produce the fault at t=0.1 s. Unless otherwise indicated, the results shown in this section pertain only to the contribution of the left-side AC system, with the measuring switch connected between the series coupling transformer and bus 3. The instant at which the series voltage is inserted was arbitrarily chosen. According to the tests carried out, it can with no restrictions be inserted at the very beginning of the fault.

4.1 SSSC case

Observe in Figure 8, the limiting effect of the series voltage (V_q=0.3 pu, inductive) when inserted to the line at t=0.20 s. Should a capacitive mode of compensation of the voltage V_se be injected prior to the fault, the line fault current would increase as the relation V_q/I_L will be seen by the system as a capacitive reactance which reduces the equivalent impedance of the line. This deleterious effect of capacitive compensation during faults, should also be taken into consideration.

On the other hand, a study regarding possible harmful effects of the short-circuit current upon the converters is also recommended to be performed, since the sudden increase of the line's current could be hazardous for the series inverter, specially if maintained for prolonged periods. Recall that the fault withstanding capability of the series VSCs depends mainly on the characteristics of the power semiconductors within the inverters (Moran, 1996).

4.2 UPFC case

If during the fault period the series angle is set to operate with a value within the range q_se=120º ® 180º, a large series inductive reactance will be emulated, hence, a significant reduction of the short-circuit current, will be achieved.

The pre-fault angle of bus 3 is 15 degrees, which means that the referred voltage, thus the total fault current, can be minimized through an angle q_se=165º; whereas to minimize the left equivalent contribution, an angle equal to q_se=180º in opposition to the 0º (degrees) of the left equivalent voltage, would be needed. The UPFC response towards the tripolar short-circuit current, is shown in Figure 9. The three-phase fault currents shown in Figures 8 and 9 were reduced in approximately 30%.

4.3 Shunt Converter Contribution to the Fault Current Limitation

As for the UPFC case, an additional strategy can be used to limit the fault current. Such a strategy consists in utilizing the shunt converter (VSC-1) so as to force the voltage, at the point where this converter is connected (therefore at the fault point), to reduce its magnitude. The total reduction of the short-circuit current in the left-side of the circuit goes from 16.66 pu (fault current amplitude in the time interval t=0.20 ® 0.30 s) down to approximately 10.82 pu (Figure 10). This represents a reduction of about 44.58% in relation to the peak-to-peak current value existing during the no fault condition. The first limiting stage (t=0.30 ® 0.40 s) pertains to the series voltage action (VSC-2), whereas the second one (t=0.40 ® 0.50 s) to the effect of the shunt converter (VSC-1). This reduction strategy does not necessarily have to follow the sequence shown in Figure 10. In fact, both compensators should act simultaneously for a more effective fault current reduction.

The elapsed time with fault (t=0.20 ® 0.30 s.) prior to the application of the series voltage, has also been chosen arbitrarily. It by no means indicates that this will be the time needed by the FACTS devices to respond or become effective. Actually, in order to avoid problems with the conventional protection system, this strategy should be applied at the onset of the fault. In this way, the current limitation effectiveness will only depend on the stress that the semiconductor switches can withstand. Also, this current limitation strategy may imply both an appropriate rating of the converters and the strengthening of the series coupling transformer's iron, so as to avoid saturation.

4.4 UPFC Phase-to-Ground Fault

The results corresponding to the phase-to-ground fault analysis developed in Section 2, regarding the equivalent positive and zero sequence impedances of the left and right AC systems, are illustrated in Figure 11.

The total fault currents are reduced from 27.20 pu (uncompensated) down to about 23.05 pu and 19.25 pu, when the positive and the zero sequence voltages (V_se1 and V_se0) are applied, respectively. For this specific system, the series angles used were q_sea=165º, q_seb=45º, q_sec=285º (for the positive sequence application) and q_sea=q_seb=q_sec=165º (for the zero sequence application).

4.5 Further Comments

The three-phase faults simulated in the ATP program were applied to a balanced system. Likewise, the converter topology corresponded to a common neutral-point clamped three-level VSC converter. That is, no special type of converter was built. For practical applications, it would be advantageous to implement 2-level VSC-based converters. Although, as reported by Schauder et alii (1998) a 3-level inverter configuration (as the one utilized in the AEP Inez Station) could also be feasible and advantageous for real world applications. The use of 3-level inverter configuration is also becoming more common for assessing the FACTS devices' response in the research stage (Dufour and Bélanger, 2005; Ooi et alii, 1999).

Of course, for phase-to-ground and bipolar faults the negative and zero sequence components must be incorporated in the ATP program. For both unbalanced systems and faults, it will be essential to have capability to inject different voltage phasors into all three phases, this research is currently underway.

Both shunt and series inverters have PI (Proportional-Integral) type of controllers that compare the reference (specified) parameters with those existing previously in the system. Also, the PLL (Phase-Locked Loop) controller used has no particular features. However, the idea while adjusting it was to find some PLL constants robust enough to operate under both normal and fault conditions, rather than building extra control systems aimed only to fault current limitation. For a proper operation of the converter (case of unbalanced systems) the PLL should be able to track adequately each phase (Song et alii, 1999; Kaura et alii, 1999).

The primary objectives of the FACTS devices regarded herein are the power flow control and the line voltage support. The short-circuit limitation strategy explored, showed that the SSSC and the UPFC may offer a useful additional functionality when implemented within the network.

5 CONCLUSIONS

This paper covered the main aspects of the steady-state AC series voltages when inserted into the power system during fault conditions. It has been observed that, aside of the power flow control characteristic and line voltage support, the series connected VSC-based devices considered (SSSC and UPFC) could be effective tools for limiting fault currents rather than being by-passed during such periods. Both devices may well overcome the continuously increasing short-circuit currents, resulting from the system expansion, which may jeopardize the fault current withstanding capability of existing assets.

The paper presented the basis to manipulate the series voltage in order to get the maximum effect while limiting short-circuits. Although in the analysis it was focused mainly the three-phase and line-to-ground faults for total and partial (branch contribution) fault currents, it could easily be extended to other type of faults. It has been shown that the UPFC shunt converter can also contribute to the reduction of the fault current. This can be achieved by forcing the line voltage to reduce its magnitude, thus, the fault current will do so. The magnitude of the series voltage used along the work was limited to 0.3 pu. The possibility to use higher values during short periods, could be translated in a more efficient compensation effect upon the short-circuit current. This aspect is still being investigated.

Artigo submetido em 18/08/2005

1a. Revisão em 03/11/2005

2a. Revisão em 27/06/2006

3a. Revisão em 30/10/2006

Aceito sob recomendação do Editor Associado Prof. Carlos A. Castro

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Publication Dates

• Publication in this collection
  02 Apr 2007
• Date of issue
  Dec 2006

History

• Reviewed
  27 June 2006
• Received
  18 Aug 2005
• Accepted
  30 Oct 2006