A multiprocessed reconfigurable architecture aimed at physical implementation of Petri Nets has been developed in VHDL, and mapped onto an FPGA. Conventionally, Petri nets are described with a hardware description language at the register transfer level, and a high level synthesis process is used to generate the boolean functions and the state transition tables needed to map them onto an FPGA (Morris et al., 2000) (Soto and Pereira, 2001). The proposed architecture has reconfigurable logic blocks especially developed for the implementation of the places and transitions of the Petri net, so, neither it is necessary to translate the Petri net model to obtain descriptions at intermediate abstraction levels, nor a synthesis process to map the net onto the architecture is in order. Petri net models that can tell tokens apart as well as Petri nets with timed transitions can be implemented. The architecture comprises a reconfigurable array of processors, and a dynamic communication system connecting the processors of the array. Each processor of the array represents the behavior of a Petri net transition, and the communication system has a number of routers to direct data packets among the processors. The proposed architecture was validated on a 10,570 logic elements FPGA with Petri Nets of up to 9 transitions and 36 places, achieving 15.4ns latency and 17.12GB/s throughput with 64.58MHz clock frequency.
Reconfigurable Architecture; FPGA; Systems Synthesis; Petri Nets
