Analog Electronic Circuit Synthesis Using Simulated Annealing and Geometric Circuit Evolution

Abstract This article presents the SANN-GCE algorithm, a spice simulation driven meta-heuristic to design general discrete analog electronic circuits automatically, both circuit topology and component sizing. We introduce an encoding scheme called Geometric Circuit Evolution (GCE) that works associated with the Simulated Annealing algorithm and uses categorized degrees of freedom, that allows distinct characteristics of a circuit to change with different probabilities according to its type during the circuit evolution. We show through a series of seven active test circuits that SANN-GCE, compared to a benchmark, present a median fitness 15.88 times better, with a median standard deviation 6.72 times lower between runs. The median runtime found was 14.17 times lower.


I. INTRODUCTION
The manual design of analog electronic circuits requires expert knowledge and many iterations of testing and optimization until a circuit with the desired characteristics is obtained.
Electronic Design Automation (EDA) software tools are commonly used for schematic capture, circuit simulation and layout, helping the designer to reach a good solution in less time.Circuit schematics are typically created based on expert knowledge.Its increasingly stringent design requirements result in more complex circuits, a problem that could be alleviated with an additional level of automation: automatic circuit synthesis.
The problem of automatically constructing a circuit can be divided in two parts: 1) Topology synthesis: determines the quantity and types of electronic components in circuit, as well their interconnections.It is a very difficult combinatorial problem, as the search space is huge and a simple change of a single variable like the connection of a component terminal can completely alter the circuit behavior.2) Sizing: involves determining the parameters of all circuit components, e.g, the value of resistance in resistors.They are usually continuous parameters of the components previously arranged in a circuit.Some commercial EDA tools have the ability to automatically optimize the sizing based on user specified desired performance target.and its modular parts.Then the Section III presents the simulated annealing algorithm, followed by Section IV that describes the Geometric Circuit Evolution, a proposed new solution representation that encodes a candidate solution in a convenient format for the simulated annealing to work efficiently.Next, the Sections V and VI shows how a problem should be designed in SANN-GCE and how its spice simulation works.It is presented in Sections VII and VIII seven test circuits as use cases for the algorithm, followed by a discussion of its results and some comparisons with other algorithms.In Section IX the final remarks of this work was reported.

II. ANALOG ELECTRONIC CIRCUIT SYNTHESIS FRAMEWORK
A framework called circ_autoproj was built from scratch to run the optimizations.The software was written in C++ using its object-oriented paradigm.The framework has a modular architecture, with two main parts loaded at runtime as plugins according to a user configuration: 1) Search Algorithm (SA); 2) Solution Representation (SR).These parts have a standardized interface that allows for a seamless exchange of plugins, thus providing agility for comparing different algorithms.
The role of SR is to construct candidate solutions objects.Each object has a method to get its fitness, and methods to modify it, like the mutation operator.The SR itself loads another plugin at runtime: the problem.It contains specifications of the desired characteristics of the electronic circuit to be automatically designed, such as the spice analysis type, the desired input/output relation, its fitness function and the test fixture.
SA is normally a meta-heuristic algorithm that holds SR candidate solutions and evolve them over time, invoking methods provided by the SR.This is the part that drives the optimization.
The framework asks SA periodically to get the best solution found so far, and record this along with various statistics in an output file.This modular construction allow decoupling the parts, and helps the developer to improve one independently of the other.
In this article, the circ_autoproj has been configured to use a simulated annealing algorithm as the SA, and the GCE as the SR.

III. SEARCH ALGORITHM: THE SIMULATED ANNEALING
Simulated Annealing [14] is a well known classic meta-heuristic for global optimization that operates on one candidate solution at a time (in contrast with population based algorithms, like Genetic Algorithm).It is suitable for applications where objective function evaluation is complex and not explicitly known (black box problems).Its main advantages are simplicity and low memory usage, as it operates on one candidate solution at a time [15].
Its operation is based on an analogy with the annealing process in solids, which comprises heating the material and then slow cooling it in a controlled way.This process allows the material domains to be reorganized into a low energy state.The statistical mechanics unveil the theory behind this physical process, and it states that the probability of the solid being in an energy state E s = E is given by (1), where Z(T ) is a normalization factor, T is the temperature and k B is the Boltzmann constant [16].
The Simulated Annealing uses the Metropolis criterion [17] to evolve its solution.This states the probability of accepting a new solution according to its fitness difference from the current solution (∆F = F new − F curr ).If the new solution is better, keep it.If it is worse, it will be accepted with a probability of e −∆F/T , otherwise the current solution is maintained.This probability of acceptance is based on Boltzmann distribution, related to aforementioned physical annealing process [18].
The Simulated Annealing algorithm used in this work is shown in the Algorithm 1.It starts with a higher temperature T = T 0 and a random candidate solution S 0 .At each iteration a neighbor solution S 1 is created from a mutation from S 0 .If S 1 is better than S 0 , makes the S 1 the current solution, decrease the temperature T by a factor α and proceed to the next iteration.If it is worse, uses the aforementioned Metropolis criterion to decide its acceptance.
Note that the higher the temperature (present in the start of the run), more likely a worse solution will be accepted.As the iterations advances, this probability fall as the temperature decreases.When T approaches zero, the Simulated Annealing becomes similar to the Monte Carlo algorithm [15].
The cooling schedule used in Algorithm 1 was the geometric cooling rule, given by T new = αT old , where 0 < α < 1 is a constant called cooling factor usually very close to 1. Additionally, when the temperature drops below the reheating threshold T r , the temperature is adjusted back to the initial temperature T 0 .
In order to keep the best candidate solution found along the evolution process, elitism was included in the Algorithm 1.It compares the fitness at each iteration and stores the best solution in a side variable S B , which is returned at the end of the run.
In this work, the stopping condition of the algorithm was set as a maximum number of fitness function evaluations, detailed in Section VII.

IV. SOLUTION REPRESENTATION: INTRODUCING THE GEOMETRIC CIRCUIT EVOLUTION
The Solution Representation (SR) encodes a candidate solution in a convenient format for the SA to work efficiently.In this work, a SR called Geometric Circuit Evolution (GCE) was developed.The main objects of an electronic circuit E in GCE are: B -the board and C = {c 0 , c 1 , . . ., c n } -an array of components.
The board represents a matrix of fixed dimensions M × N .Each position are circuit-equivalent as electrical contacts -pads -insulated from each other, resembling somewhat a rectangular perforated circuit board.A board position can have zero or more component terminals associated with it.The Fig. 1 shows an example of a GCE board filled with some components.return SB ▷ return the best solution found 36: end function A board, as an object, stores: • number of components in the circuit (n); • an array of n component objects; • Ω = {ω n0 , . . ., ω nx , . . ., ω np }, a set of sets, each containing a fixed node nx attributed to some external pads.For example, the set ω n0 = {(2, 0), (2, 1), (2, 2), (2, 3)} indicates that those four pads are associated with the external node 0, the GND in the spice simulation.These external nodes are depicted as dotted areas in Fig. 1.
Each component c in GCE stores: • Its type (for example: resistor, transistor, etc.); • The position for each of its terminals on the board; • Its parameters (for example: electrical resistance, model of a BJT transistor, channel width in a FET transistor), stored as an array of variant data type (integer, float or string depending on parameter type).Each object in the GCE may have some chosen variables that can be perturbed from the outside.Those variables are called here degrees of freedom (DOF), a correspondence with mechanical systems.When a DOF is perturbed, it calls its own specific generator routine to (possibly) generate a new value and then optionally call a listener routine to act on the value changed.For example, the parameter n of the board (the number of components of the circuit) are a DOF that, when perturbed, generates a uniform distributed random number in a range [min, max] and then creates or destroys a number of components to hold exactly n components in memory.

Component ct=R
Terminal The position of each of the two terminals of the resistor In the first generation, a uniform distributed random integer within the allowable range is returned.Later generations increment each axis independently by -  • Discrete: defines a discrete variable (e.g. the spice model of a transistor, chosen from a list of options).Its change may imply in moderated variation in circuit response; • Structure: control the structure of the circuit (e.g. the number of components).Its change may cause great variation in circuit response, and can alter the number of DOFs.
Table I lists all DOFs used in GCE, along with its type, their pertaining object, its description, the possible values it can take, generator and listener details.
The main interface between GCE and the SA is the mutation procedure, invoked by SA in GCE.No crossover operator was used.The mutation acts in the GCE's DOFs according to the Algorithm 2.
The procedure obtains all the DOFs and visit them one by one.In a visit the DOF may be perturbed (i.e.mutated).Note that structure type DOFs are processed first in a special way, because when perturbed it can create or destroy other DOFs.The mutation occurs with a probability p m = p mg • p s (T ), where p mg is a general mutation probability and p s (T ) is a specific mutation probability for the DOF type T .Both p mg and p s (T ) are configurable parameters.
The discrimination of p s (T ) for different T allows the mutation to be less frequent for the types of DOFs that, when perturbed, can cause disruptive variations in the circuit response.In this way, the search algorithm can explore the problem space more efficiently.if T = structure then 6: if R( ) end for 21: end procedure A candidate solution creation starts with a board object with its only DOF (n, the number of components, structure type) set to zero.This DOF is perturbed, which causes n to assume a positive random value n min ≤ n ≤ n max .Its listener routine acts on value changed, creating n component objects (each one adding DOFs to the candidate solution).Each component in turn will have its DOFs perturbed, starting by the structure type DOF c t (component type), which will define the component type and create its specific DOFs.Then, all the remaining components DOFs are perturbed, resulting in a random electronic circuit.

V. PROBLEM FORMULATION
The circuit to be synthesized in SANN-GCE must be prescribed through a problem formulation, which involves the following steps: • Defining a test fixture (TF), that is a fixed circuit that supply power and tests the circuit that will be created -called here evolved circuit (EC).The interface between TF and EC are the external nodes; • Specifying the manipulated variable(s) (MV).This is the TF circuit parameters that are changed in order to test the EC; • Prescribing the responding variable(s) (RV).This is usually voltage or current in TF node(s) that indicates the EC response to the stimulus given by the MVs; • Writing the spice script that drives the simulation, based on the previous items of this list.The script must contain the type of analysis to run and the variables to be saved for the fitness calculation.

It may contain component models and simulation options;
• Writing the fitness calculation function.Its input is the spice simulation output, normally a collection of arrays.This will be compared with a desired reference output, giving a real number representing a fitness of the EC.The lower the fitness, the better the circuit.This is the primary metric, the only that drives the meta-heuristic optimization; • Writing secondary metric functions.This is optional, and is also calculated comparing the spice simulation output with a desired reference, but using other formulas.This is just to be logged and is not used in the meta-heuristic optimization.

VI. CIRCUIT SIMULATION
The candidate solutions are assessed in order to get some performance metrics of each one.The main metric that drives the evolutionary process is fitness f , which the smaller the better.Thus, the objective of the meta-heuristic is to optimize the circuit, minimizing f .The calculation of fitness is obtained through the following steps: 1) Obtain the raw spice netlist S ′ from the candidate solution E, using the Algorithm 3; 2) Pre-process S ′ .This comprises: sequentially numbering the components and removing components that have all their terminals short-circuited.The result are saved in S; 3) Run spice simulator with netlist S as input.The result are θ, a data structure that contains vectors for the voltages and/or currents requested for some or all circuit nodes over time, frequency or temperature, depending on the type of spice analysis requested; 4) Process θ to obtain f and some other metrics, using the problem's objective function P ().
The spice simulator used in this work was the Ngspice [19], an open source and multi platform circuit simulator compatible with PSPICE and LTSPICE.

VII. TEST CIRCUITS
In order to test the SANN-GCE, it was selected seven problems (test circuits) as use cases for the algorithm.These test circuits are the same as in [10] and [12], because they presented seven different use cases with detailed results, and all tests were run 50 times, which allowed us to make a robust comparison.
The test circuits was divided in two sets: 1) Non-computational circuits, which comprises a temperature sensor circuit, a Gaussian function and a voltage reference; 2) Computational circuits: squaring, square root, cubing, and cube root.
Table IV shows the SANN-GCE parameters used in each test circuit.These parameters were chosen after preliminary runs with different values for each parameter.The best combination found experimentally are used in each test circuit.The experimental nature of the parameter tuning is typical in metaheuristics algorithms [20].Fine-tuning each parameter for each test circuit was outside the scope of this work.
Each candidate solution is accessed to get its primary and secondary metrics.Equation ( 2) calculates the fitness value f , the primary metric that drives the optimization algorithm.
where N p is the number of points in the result of the spice simulation, and e i is the absolute error between the circuit responding (output) variable X i and the desired (reference) value Xi , calculated as follows: The w i is a weight factor that increases the penalty to the fitness f when fitting points has an error above a predefined threshold X th : The w b is a base weight that can be configured in each test circuit.Other metric calculated is the Mean Average Error (MAE), a secondary one, obtained as the following: Other secondary metric was the hits %.This calculates the percentage of fitting points that has an error below the threshold X th : Table II presents the values of some of the variables referenced in the above equations for each test circuit and the following Sections describe each test circuit in detail.

A. Temperature sensor
The temperature sensor problem aims to automatically design an analog electronic circuit that generates an output voltage proportional to the circuit temperature.See Fig. 2 for the test fixture used in this problem.The spice simulator changes the circuit temperature following the sequence T = [0, 5, 10, . . ., 100], resulting in N p = 21 simulation points.The circuit output is the voltage in node #3, denoted as X i , where i is the corresponding point in the input vector T .The desired output is given by Xi = T i /10.

B. Gaussian function
The Gaussian function circuit tries to make its output current approximate a Gaussian curve as a function of the input voltage.The Fig. 3 presents the test fixture used in this circuit.The input source change its voltage linearly as V in = [2, 2.01, 2.02, . . ., 3], resulting in N p = 101 simulation points.The output X i is the current flowing out to node #3.The desired output for the i-th input is given by the Equation (7), where a = 80 × 10 −9 is the peak value of the function, b = 2.5 is the distribution average value and c = 0.1 is the standard deviation. ( Vsrc Fig. 3. Test fixture for the Gaussian function circuit.External node numbers are between parenthesis.Manipulated variables are between angle brackets and responding variables are between square brackets.

C. Voltage reference
The voltage reference circuit tries to keep its output voltage constant when subjected to variations in supply voltage and circuit temperature.Its test fixture is depicted in Fig. 4 Therefore, R < 1 and R > 1 means, respectively, a worse and a better result for SANN-GCE, regardless of whether a particular metric follows the logic of smaller is better or greater is better.
The SANN-GCE performance ratio regarding ACID-MGE was calculated individually for each metric in all test circuits.Then these data were grouped by metric and shown in Fig. 6 as a boxplot, to facilitate comparison between SANN-GCE and ACID-MGE.It can be seen in Table V that SANN-GCE have a consistent performance advantage in various metrics, such as in SR%, BF (mean and standard deviation), hits (mean and standard deviation) which are better in 100% of test circuits when compared to both ACID-MGE and ACID-GE.
Fig. 6 presents that, compared to ACID-MGE, SANN-GCE has a median performance ratio for SR% equal to 1.5, calculated over all the test circuits.For BF mean it was 6.72.In BF SD the median was 15.88.Hits mean and Gen mean was both 1.06, Hits SD was 3.77.NCBC was 1.2 and Runtime was 14.17.
Continuing with the same analysis method described above, SANN-GCE was worse than ACID-MGE in the MAE (mean, standard deviation, min), BF min and Gen SD metrics, with a median of R equal to 0.73, 0.62, 0.81, 0.91, 0.86, respectively.
These results shown that the SANN-GCE have a notable performance, specially lower variability between runs (BF SD ) and also good mean value (BF mean ) for the primary metric.
The runtime also stands out, with a median 14.17 times faster than the ACID-MGE.This result must be taken with care due to the inherent differences of hardware and software, but we can say that the simplicity of Simulated Annealing played an important role in this regard.As stated before, it uses only the mutation operation to modify a candidate solution, unlike others algorithms that also uses the crossover operator, such as ACID-GE/MGE which are based on genetic algorithms.
We attribute the two favorable results in the primary metric to the slow and incremental nature of the SANN-GCE algorithm for using mutation only, compared to the more disruptive crossover operator used in ACID-MGE.This may also explain the slightly less favorable BF min obtained in our algorithm: the higher level of search space exploration done in ACID-MGE by its crossover operator might be able to more easily achieve a better fitness during optimization.

IX. CONCLUSION
In this paper we presented GCE, a new solution representation for simulation based analog electronic circuits, working together with simulated annealing, a classic meta-heuristic for optimization.The GCE internally represents a candidate solution as a collection of objects, with components placed geometrically on a board similar to a physical perforated board.
It was demonstrated that our algorithm can be used to successfully design analog electronic circuits automatically using a mutation-only approach, using only one candidate solution in each generation.
Using only the mutation operator made the algorithm simpler and resulted in low resource usage, as it operates on one candidate solution at a time.This may explain the fact that the median runtime was 14.17 times faster on SANN-GCE when compared to ACID-MGE.
SANN-GCE was tested with seven test circuits, and for each one, 13 metrics was collected and discussed.The results showed good performance in various metrics, specially consistent performance between runs, showing lower standard deviation than the others algorithms compared (e.g. in median, SANN-GCE have the standard deviation of BF 15.88× lower than ACID-MGE.For Hits it was 3.77× lower).In real use this means that we could get a circuit with reasonable performance with fewer runs.Also, for metrics SR%, BF (mean and standard deviation) and hits (mean and standard deviation), SANN-GCE was better in all circuits tested.
The algorithm parameters used in this work were chosen experimentally after few trials and was not investigated in details.Their influence on algorithm performance needs further investigation and is planned as a future work.

APPENDIX 1 -PARAMETERS AND RESULTS
In this appendix we show Fig. 7 and Fig. 8 with the performance curves of the best circuit found in each problem.We also present Table IV and Table V, one showing the parameters used in the test circuits and the other containing the results.

Fig. 1 .
Fig. 1.GCE board example.The gray squares are the board pads and the dotted areas point to the external nodes.Multiple pads inside the same external node are short-circuited.

All
DOFs have an associated type T , which can be one of the following:• Terminal: represents where a terminal of a component is connected in the circuit.Its change may have great variation in circuit response;• Continuous: defines a continuous variable (e.g.resistance of a resistor).Its change may have smooth impact in circuit response; Brazilian Microwave and Optoelectronics Society-SBMO received 7 July 2022; for review 11 July 2022; accepted 5 Jan 2023 Brazilian Society of Electromagnetism-SBMag © 2023 SBMO/SBMag ISSN 2179-1074

Fig. 2 .
Fig. 2. Test fixture for the temperature sensor circuit.External node numbers are between parenthesis.Manipulated variables are between angle brackets and responding variables are between square brackets.

Fig. 6 .
Fig.6.Performance ratio between SANN-GCE and ACID-MGE in each metric.The statistics for each metric was calculated over all test circuits.Values > 1 denotes SANN-GCE better.The numbers above each box are the median.

TABLE I .
LIST OF DEGREES OF FREEDOM IN GCE ct Component Structure The type of the component ct ∈ {R, Q, M a}, where R is a resistor, Q is a bipolar junction transistor (BJT) and M a is a MOSFET with fixed channel length of 10 µm Choose randomly from the prescribed set of discrete values, with specified individual weights.Listener routine: Regenerate all specific component DOFs crta, cr tb Journal of Microwaves, Optoelectronics and Electromagnetic Applications, Vol.22,No. 1, March 2023 DOI: http://dx.doi.org/10.1590/2179-10742023v22i126577520All the information needed to express it as a spice netlist are contained inside the object's DOFs.This operation are called translation, and are depicted in Algorithm 3. The candidate solution netlist are then sent to the spice simulator in order to get its performance.Section VI presents the details of this step.Each component type must implement the method get_netlist().Require: START_NODE: integer that states the first node number to use in the internal nodes Require: get_external_node(P ): function that return the external node number (≥ 0) for the board position P or −1 if P

TABLE II .
PARAMETERS FOR CALCULATING THE METRICS FOR TEST CIRCUITS

TABLE V .
RESULTS OF THE SANN-GCE ALGORITHM COMPARED TO ACID-MGE AND ACID-GE.LESS IS BETTER FOR ALL METRICS, EXCEPT THOSE MARKED WITH AN ASTERISK (*).THE BEST RESULTS FOR A METRIC IN EACH TESTCIRCUIT ARE IN BOLD.