This paper presents a power-efficient RF differential receiver front-end supporting transmitted-reference (TR) communication in a 90 nm CMOS technology. Particularly, it addresses the issues of designing the frontend amplifier with low-noise and passive matching circuits on a silicon process and integrating a low-power delay unit in the front-end with wideband characteristics. The proposed architecture includes a differential high simulated gain (11 dB) amplifier which is centered at 21.6 GHz (in the K-Band) with a 6.2 GHz bandwidth (18.1~24.3 GHz). The input and output reflection parameters have centered values around -26 and -18 dB, respectively. With noise matching, the amplifier achieves 2.6~2.9 dB bandwidth noise-figure and 2 dBm input power limit for linear coverage. To interface the amplifier with a following RF mixer, a submicron delay-block (DB) is proposed with provision of adjusting number of stages in the delay chain. The branched DB architecture achieves monotonic delays covering a range of 70-800 ps (including group-dispersion). Tweaking of delay is possible through four design parameters and the set-up is analyzed by extending the number of cascaded stages up to eight. Driven from a 1.2 V supply, the amplifier and the DB consume 13.9 and 8.52- 10.61 mW power, respectively, and realize the circuits for the TR front-end. When compared with simulated results of reported CMOS receivers, the proposed design delivers higher performance in terms of a microwave figure-of-merit.
CMOS Front-End; TR; Differential Amplifier; Delay-Block
