Board level solder joint analysis of ball grid array package under drop test using finite element methods

ABSTRACT

Handheld electronic devices are vulnerable to drop impacts, leading to mechanical damage and electrical failures such as PCB cracking, trace damage, solder joint fractures, and component breakage. This study investigates the reliability of solder joints in Ball Grid Array (BGA) packages by examining their dynamic response under board-level drop impacts using Finite Element methods. Explicit dynamic analysis employing the Input-G method, in accordance with JEDEC guidelines, was used to simulate the printed circuit board assembly (PCBA) model. Results reveal that solder balls on the board side are more critical than those on the package side, with corner-most solder balls near the board edges identified as the most vulnerable, experiencing maximum peel stress of 162.12 MPa and strain of 0.001048. Analysis of radial displacement and drop orientation showed that BGA packages positioned closer to PCB edges exhibit greater reliability than those at the centre. The face-down drop orientation was identified as the most vulnerable configuration. Structural optimization of the PCBA, incorporating factors such as solder ball pitch, PCB thickness, and solder ball diameter, significantly improves reliability, underscoring the importance of these parameters in ensuring the long-term durability of the assembly.

Keywords:
Board level reliability; BGA package; Surface Mount Technology (SMT); Parametric Analysis; Drop Test; Solder ball

1. INTRODUCTION

A major worry for the consumer electronics sector is solder joint failure in devices when exposed to shock and drop environments. The current trend of downsizing and higher functional density has led to a decrease in the I/O pitch, which raises the possibility that the Integrated circuit will break in shock and vibration settings. Also Mishandling during shipment or customer use may result in mechanical shock that breaks the solder joint, which causes the device to malfunction, as the impact force of a dropped electrical device is transferred to the PCB, solder joints, and packaging. A combination of the mechanical shock from collision and the bending of the printed circuit board (PCB) causes solder joint failure. Thus, to reduce the influence of shock on the solder joints, during impact, design optimization of the printed circuit board assembly (PCBA) is required. Ensuring system reliability and robustness is crucial in enhancing efficiency and maintaining high standards in modern manufacturing operations [¹,²,³,⁴]. The JEDEC test standard JESD22-B111A, outlines procedures for conducting board-level drop tests and aims to assess and compare the performance of surface mount electronic components in handheld electronic products through an accelerated testing environment [⁵]. Under this standard, board-level reliability of components under drop test is addressed by exposing the board to an impact pulse using a shock test tower. However, since the actual product boundary conditions and impact orientation may differ from the test configuration, it is often challenging to infer product-level performance from the board-level JEDEC test. Dynamic responses like Input acceleration, output acceleration, deformation, strain in the PCB, solder ball and the package act as crucial parameters in evaluating the failure of solder joints. Numerous studies involving experiments and simulations of drop tests were conducted following JESD22-B111 guidelines for various PCB and solder ball configurations to evaluate the performance of solder joints [⁶, ⁷]. The actual drop testing is costly, time-consuming, and require much more resources in measurement and failure analysis. The finite element (FE) model is straightforward and efficient, demonstrating a strong correlation with experimental testing in dynamic responses like output acceleration, stresses, and strains [⁸, ⁹]. Various explicit modeling techniques such as sub-structure modeling (super element) and global/local modeling (sub-modeling), were developed and explored for simulating shock loading on PCBAs [¹⁰]. CHUNG and KWAK [¹¹] has researched the reliability of BGAs with various structural designs for Printed Board Assembly mounting, establishing characteristic life and failure models for drop reliability. An effective approach for representing solder interconnects as beam elements in FEA is also proposed, providing a model that is both relatively simple and detailed. The simulations conducted using the Input-G specified by JESD22-B111 showed strong correlation with the experimental results [⁶]. By analyzing the variations in dynamic voltages, YUAN et al. [¹²] had established, a relationship between drop times and the stages of package failure, using the dye penetration method to observe the internal crack and failure locations. The product-level reliability of portable electronic devices under drop impact was investigated, and the dynamic responses of the devices at various impact forces and orientations were studied through experiments [¹³]. BENDER et al. [¹⁴] reviewed trends in microelectronic packaging reliability testing, emphasizing methods initially developed for older packaging assemblies and adapted for advanced packaging schemes. The study aimed to identify testing practices with high potential for success, considering the increased complexity and variety of hybrid bonds in modern packaging. Chang’s work underscores the importance of evolving testing methodologies to ensure reliability in emerging packaging technologies. YUNUSA [¹⁵] evaluated solder joint reliability using finite element analysis, focusing on thermo-mechanical fatigue-induced failure, by analyzing three variations of the BGA package with the SAC305 lead-free alloy. WONG et al. [¹⁶] developed an analytical model to quantify the distorted responses of a PCB under drop testing using Fourier series. The magnitude of the distortion in the PCB’s response was expressed as the magnitude of distortion in half-sine excitation. Mechanical reliability of Sn–Bi solder paste and Sn–Bi composite solder paste with thermosetting epoxy (TSEP Sn–Bi) was evaluated through board-level drop tests showed that TSEP Sn–Bi solder joints exhibited reduced failure rates, with drop durability increased by 1.55 to 3.00 times compared to Sn–Bi solder joints [¹⁷]. Impact of system design and testing conditions on the dynamic behavior of solder balls in components using finite element analysis was studied and the model was extended to new configurations that explore component placement, secondary attachment, and drop orientations at the system level [¹⁸]. Through experimentation, key parameters including PBGA assembly fatigue life, the relationship between solder joint positions and fatigue life, and the relation between strain energy density and fatigue life are analyzed [¹⁹]. SAC305 solder joints in BGA-packaged chips were analyzed using random vibration tests and finite-element simulation. Findings show that solder joint life follows a lognormal distribution, with the outermost solder balls under greatest stress and prone to cracking near the IMC layer edge with the largest curvature [²⁰, ²¹]. The failure mode and mechanism of solder joints under board-level drop impact in leaded and lead-free solder balls were investigated using a rate-dependent material model. It was concluded that the selection of the life prediction model depends on the failure mode of the solder joints [²², ²³]. The role of simulation-based reliability prediction and structural optimization in improving solder joint thermo-mechanical performance was carried out by combining empirical testing and simulation. Thereby refining design parameters, guiding the selection of optimal solder materials and packaging designs to enhance the longevity and reliability of electronic components [²⁴, ²⁵]. A new approach integrating deep learning and FE analysis for solder joint quality assessment, enhancing reliability in autonomous systems. The ML method offers efficient, accurate predictions of BGA packaging dynamics, replacing traditional FE modeling [²⁶,²⁷,²⁸,²⁹].

Although FE models and explicit modeling approaches have been used, there are still gaps in its effective integration with optimized testing protocols and design enhancements for PCBA. Inadequate predictive capacities for strain, deformation and dynamic reactions during mechanical shocks limit the capacity to create dependable product design. There is an urgent need for increased reliability forecasts, optimal material selection and sophisticated testing frameworks to minimize the incidence of solder joint failures. Moreover, inadequate optimization of critical PCBA components to reduce solder joint failure under drop impact in most studies is observed.

In this proposed research, an explicit dynamic analysis of PCBA, using input-G method, is carried out and the location of the maximum stress are identified as the regions which are vulnerable to failure. Also, the impact of radial displacement of Ball Grid Array package from the center of the PCB and drop orientation of the PCBA, on the solder joint failure are studied. This paper also presents a thorough parametric study of the geometrical and material properties of the assembly like PCB modulus, PCB thickness, solder ball diameter, solder ball pitch, substrate thickness, substrate modulus, silicon thickness under shock.

2. MATERIALS AND EXPERIMENTAL METHODS

2.1. Mechanics of board level drop test

The assurance of board-level drop test reliability for surface-mounted components is mandated by JEDEC standards [⁵]. Within this framework, package reliability is evaluated experimentally using a drop test tower setup. In this experimental setup, a printed circuit board (PCB) with components facing downwards is affixed to a base plate via connectors, as depicted in the Figure 1.

Figure 1
Experimental setup of drop test.

The base plate undergoes free fall along guide rods, ultimately impacting a solid foundation through cushion pads, known as the shock generator. By adjusting the drop height and the stiffness of the shock generator, the base plate is subjected to a half-sine wave acceleration profile to investigate joint failures in the mounted component. However, conducting actual drop tests is both costly and time-intensive, demanding significant manpower for measurement and failure analysis. In the competitive telecommunications sector, modelling has emerged as a highly efficient alternative in IC packaging for design analysis and optimization, particularly when compared to conducting actual drop tests.

Numerous studies have confirmed a robust correlation between experimental findings and simulation results for drop impact tests conducted at the board level [⁶, ⁷]. The present study has adopted the Input-G method to simulate and assess the board level impact performance, as prescribed under JEDEC22-B111A [⁵]. The Input-G method is adaptable to various configurations of PCB mounting. While it doesn’t directly simulate the base plate, fixture, connector, or friction of guiding rods, it indirectly incorporates their complex effects by utilizing the same impact pulse observed in experiments. Consequently, this facilitates the application of the same impact pulse in analyzing the design aspects of PCB/package geometry and material. Due to the simplicity of the Input-G method, its computational time is anticipated to be significantly shorter compared to conventional free-fall drop models. Consequently, the Input-G method stands out as an efficient tool for conducting Design of Experiments (DOE) studies or optimizing Package/PCB design parameters to enhance drop test performance [¹⁸]. Drop impact is characterized by the shock G pulse, which is directly applied at the mount holes using the following equation.

(1) $$A(t)=Aosin\left(\frac{\pi t}{tw}\right)$$

where A₀ is the G level, considered as 1500 g and t_w is time duration which is 0.5 ms. As per the JEDEC conditions, the drop test problem is reduced to a simple problem of the board response after a shock pulse is applied. Conducting an actual drop test for package qualification or design analysis usually involves a comprehensive process that extends beyond many productive days.

3. FINITE ELEMENT MODEL

In this paper, the performance of the board and the reliability of the solder joint is evaluated by studying the dynamic responses of solder balls. JEDEC’s specifications provide comprehensive guidelines for conducting drop tests, specifying the shock pulse duration and the boundary conditions for the test board. The explicit dynamic analysis using Input G method approach is employed using the Abaqus software to comprehensively investigate the BGA package behavior under dynamic loading conditions. Because of the brief impact duration, explicit solvers provide higher efficiency for drop test solutions when contrasted with implicit solvers [³⁰]. Figure 2 represents the geometrical dimensions of PCB, BGA package and solder balls considered for simulations.

Figure 2
(a) Design of printed circuit board (b) BGA package and solder ball.

The BGA package modeled in Abaqus software consists of the die, underfill, and substrate arranged sequentially. Underfills play a crucial role in stabilizing solder bumps, enhancing the reliability of connections, and providing structural reinforcement for delicate devices. The BGA package is then assembled on to the 90 mm × 90 mm Printed Circuit Board (PCB) via an array of solder balls. Solder balls of diameter 0.3 mm and a pitch of 1mm are considered in this configuration. Figure 3a shows the finite element model of the PCBA and Figure 3b shows the quarter geometry and the boundary conditions used in the analysis.

Figure 3
(a) Design of printed circuit board (b) BGA and solder ball.

The simulation aims to gain insights into the dynamic response of the package and performance characteristics during a drop test scenario and further, simulations are also intended to examine the vulnerability of solder joints in different locations of package, impact of radial displacement of package on the PCB, and influence of drop orientations. Furthermore, a comprehensive parametric analysis was performed on a range of PCBA geometrical and material properties. To expedite computation time, a quarter model of the package is utilized.

Dimensions and material properties of the different components of the PCBA have been detailed in Table 1. All the components were considered as isotropic elastic material properties. PCB, solder balls, and package components, were separately meshed and assembled. However, the computation process encountered challenges due to the substantial aspect ratio of the mesh size for the PCB and solder ball, coupled with the sheer volume of elements involved. The large aspect ratio and the significant number of elements resulted in an extensively prolonged computation time, causing notable delays in the analysis process. Tie constraint was used to obtain the continuity between the assembly. The model incorporates C3D8R hexahedral elements and C3D6 wedge elements, comprising a total of 148,610 nodes and 1,10,456 elements. Explicit dynamic analysis was carried out with mass scaling factor of 0.00005 and with a step time of 0.0005 ms. Dynamic performance of the PCBA model was simulated for a time period of 10 ms. Symmetric boundary conditions are assigned along the medium line of the PCB to simplify the simulation by considering the symmetric of the PCBA. The shock G-pulse is directly applied at the mount holes with a peak acceleration of 1500G applied as a half-sine pulse as indicated in Table 2, representing the dynamic load. Symmetric boundary conditions are enforced in the x and y directions as only quarter model was modeled and an input acceleration with a peak amplitude of 1500G is applied as a half-sine pulse as indicated in Table 2 to the mount holes. Figure 4 indicates the half sine pulse of 1500 g applied for a time period of 0.5 ms at the mount holes.

Table 1
Dimensions and mechanical properties of the components.

COMPONENT	YOUNGS MODULUS (GPa)	DENSITY (Kg/m3)	POISSON’S RATIO	DIMENSIONS IN mm
Die	160	2230	0.3	10 × 10 × 0.5
Underfill	20	150	0.3	10 × 10 × 0.05
Substrate	30	1850	0.3	15 × 15 × 0.75
Copper Pad	130	8830	0.3	ϕ0.3 × 0.02
Solder Ball	50	8600	0.3	ϕ0.3
PCB	30	1780	0.3	90 × 90 × 1

Table 2
Input half sine wave acceleration.

TIME (ms)	ACCELERATION (G)
0	0
0.027778	260.4723
0.055556	513.0302
0.083333	750
0.111111	964.1814
0.138889	1149.067
0.166667	1299.038
0.194444	1409.539
0.222222	1477.212
0.25	1500
0.277778	1477.212
0.305556	1409.539
0.333333	1299.038
0.361111	1149.067
0.388889	964.1814
0.416667	750
0.444444	513.0302
0.472222	260.4723
0.5	1.84E-13

Figure 4
Acceleration pulse for 1500G.

3.1. Mesh sensitivity analysis

A mesh sensitivity analysis was conducted to identify an optimal mesh size that provides accurate simulation results while minimizing computing time. Figure 5 shows the impact of variation in peel stress with the solder ball mesh size. Finer mesh increases the number of the the number of nodes per unit area or volume, allowing for more precise capture of deformation and stress. The analysis was performed at element sizes of 0.04, 0.05, 0.06, 0.08, 0.1, and 0.12 for the solder balls. However, beyond a certain element size, the output converges and becomes independent of the mesh size. This consistancy was observed from mesh size 0.06 with total number of elements 75000. Hence an optimal mesh size of 0.04 with total number of elements 1,10,456 was chosen where convergence was achieved requiring 2,800 seconds and resulting in a maximum peel stress of 162.12 MPa.

Figure 5
Mesh sensitivity.

4. RESULTS AND DISCUSSION

Through explicit dynamic analysis failure of the solder joints is identified through the areas of maximum stress. The maximum stressed areas are identified as the weakest spots where solder balls joints tend to fail. During impact, strain energy is transferred to the PCB through the connectors, resulting in the bending of the PCB. Consequently, this bending induces alternate tensile and compressive stresses in the solder balls. Thus, the curvature of the PCB serves as a criterion for evaluating solder joint performance. Simulation results reveal that the corner most solder ball of the array (closer to mounting hole) at the PCB interface experiences the maximum peel stress. Tensile stress which is also termed as peel stress experienced by the array of solder balls and the corner most solder ball during the impact is shown in Figure 6. Figure 7 illustrates the history of Peel stress (S33) experienced and logarithmic strain (LE33) in the critical solder ball for a time period of 10 ms. It is also evident from the figure that the PCB experiences alternate tensile and compressive stresses due to the flexing of the PCB. From the simulation results, the maximum peel stress experienced by the critical solder ball at the PCB interface is 162.12 MPa and logarithmic strain (LE33) in the critical solder ball 0.001048. Figure 8a depicts the maximum deflection of the PCB during downward and upward bending after impact. Figure 9 quantifies the deformation of the board near the center and near mount hole for the due to the impact. And it is evident that PCB has the maximum deformation of 1.1 mm at the center and near the mount holes it is minimum with 0.435 mm. The response of the board was observed for a duration of 10ms, with maximum deformation occurring at 1ms, after which deformation dampens. During the horizontal drop with package facing downward, the initial bend after the sudden impact creates a positive curvature (downward bending), as shown in Figure 10a, which in turn induces maximum tensile stress and successive upward bend shown in Figure 10b produces a compressive stress in the corner most of solder balls causing an eventual failure of the solder ball. Hence the same critical solder ball is the primary focus of this paper to delve into other investigations such as analyzing the positioning of mounting holes within the PCB and assessing the effects of drop orientation and parametric analysis. Due to the inherent rigidity of BGA packages in comparison to the PCB, the board’s bending, combined with the greater stiffness of the BGA package, imposes tensile forces on solder joints. These solder joints undergo cyclic peeling stress and compressive stress, leading to eventual failures. To summarize, the primary factor contributing to solder joint failure during drop impact on a PCB is the combined influence of a significant mechanical shock and cyclic bending vibration.

Figure 6
Critical solder ball of the BGA package.

Figure 7
(a) Peel stress (S33) in most critical solder ball. (b) Logarithmic strain (LE33) in the critical solder ball.

Figure 8
(a) PCB deformation during downward bending. (b) PCB deformation during upward bending.

Figure 9
Comparison of PCB deformation at the corner solder ball and the mount hole.

Figure 10
Flexing of PCB (a) PCB flexing downwards (b) PCB flexing upward.

4.1. Effect of radial displacement of BGA position

Mounting holes of the PCB ensure proper alignment and fixation of the board within the electronic device and also helps in transferring the impact energy during the drop, from the system to the PCB. Consequently, the relative position of the package on the PCB with respect to the mount hole influences the distribution of mechanical forces on the solder balls. An investigation was conducted to examine the stresses in the critical solder balls by varying the position of package on the PCB. Figure 11 presents the finite element model of a quarter board assembly for three different package locations.

Figure 11
Radial displacement of BGA (a) BGA at PCB center (b) BGA at 7×7 mm from center (c) BGA at 30×30 mm from the center.

A finite element simulation was conducted to analyze the effect of different package positions. Figure 12 shows the peel stress induced in the critical solder ball for three different positions. The maximum peel stress observed when the package is at the center, 7 × 7 mm from the center, and 30 × 30 mm from the center are 162.12 MPa, 128.12 MPa, 82.92 MPa respectively. As shown in Figure 10, during PCB flexing, the curvature gradually increases from the corners toward the center. Therefore, components placed at different locations on the PCB will experience varying effects. It is clearly evident that BGA packages located at the center of the PCB are more susceptible to failure than those placed nearer to the mount holes.

Figure 12
Peeling stress for varying mounting hole location in the outermost solder and inner most solder ball.

4.2. Impact of drop orientation

In this study performance of the board under three different drop orientations – BGA package facing downward (0° rotation) and BGA package facing upwards (180° rotation) and vertical drop (90° rotation) are analyzed. Figure 13 illustrates different drop orientations of the board, while Figure 14 shows the stresses experienced during face-down, face-up, and vertical drops. According to simulation results, the 0° drop orientation is the most severe, with a maximum peel stress of 162.12 MPa. In the vertical drop, peel stress is 0.09 MPa, which is almost negligible, but a shear stress of 11.3 MPa is observed. The maximum peel stress in the face up drop is 148.2 MPa which is comparatively lesser than face down drop. However, shear stress is negligible in face down and face up drops. During a vertical drop, the strain energy resulting from the impact causes the board to experience either elongation or compression. This elongation or compression induces shear stresses in the board. Since there is no significant bending involved in a vertical drop, the peel stress is almost negligible. Consequently, the failure of solder joints is unlikely during a vertical drop.

Figure 13
Different orientations of drop impact (a) BGA package face down (0°) (b) BGA package face up (180°) (c) Vertical drop (90°).

Figure 14
Peel stress and shear stress for face down, face up and vertical drop orientations in the critical solder ball.

4.3. Parametric analysis

A comprehensive parametric analysis was conducted on the geometrical and material properties of the PCBA as presented in Figure 15, to identify significant parameters that would substantially reduce stress in the solder joints, thereby enhancing the reliable life of the board-level assembly. Parametric analysis provides manufacturers with valuable insights into specific aspects of the PCBA design and manufacturing process that contribute to reliability challenges. The finite element model presented in Section 3 was considered for the parametric analysis, and the maximum peel stress in the critical solder ball obtained through simulation taken as the reference value. To expedite computational time while retaining accuracy, a strategy was implemented where only the most critical solder ball was densely meshed, while the remaining solder balls were meshed coarsely.

Figure 15
Peel stress variation in critical solder ball with varying (a) PCB modulus (b) PCB thickness (c) Solder ball diameter (d) Solder ball pitch (e) Substrate modulus (f) Substrate thickness (g) Silicon thickness.

4.3.1. PCB modulus

The peeling stress in the critical solder ball was monitored as the PCB modulus varied from 7.5 GPa to 90 GPa. Results summarized in Figure 15a shows a negative correlation between the peeling stress and PCB modulus. The stress was highest when the PCB modulus was 7.5 GPa, which subsided by 25% when PCB modulus is 90 GPa which is three times the baseline modulus. As the stiffness increases beyond 30 GPa, the decrease in stress becomes more gradual, following a nearly linear trend. This correlation suggests that a stiffer PCB enhances the mechanical performance of solder joints by reducing peel stress during drop, which could potentially improve the reliable service life. Dynamic deformation in PCBs, caused by vibrations and mechanical shocks, is mitigated by higher stiffness and also helping solder joints maintain their original geometry and structural integrity. However, there are constraints on increasing PCB stiffness beyond a certain value. PCBs are typically composed of resin, glass cloth, and copper traces, with moduli of 20 GPa, 30 GPa, and 50 GPa, respectively, resulting in an effective PCB modulus range of 20 GPa to 50 GPa. Metal-core PCBs, which incorporate materials such as aluminum or copper as the core, offer enhanced thermal management and mechanical stability. These properties make them potential candidates for further improving the mechanical performance of PCBs, particularly in high-power and high-thermal applications [³¹].

4.3.2. PCB thickness

Figure 15b shows that stress variation is non-linear, with a sharp drop observed as the thickness increases from 0.75 mm to 1 mm, and then tapers off gradually as the thickness increases beyond 1 mm. This indicates that the material experiences less stress as it becomes thicker. At a PCB thickness of 0.75 mm, the peeling stress is amplified by 56.63% compared to the baseline stress of 162.12 MPa. As the thickness increases to 3 mm, the stress decreased by 50%. The thickness of the PCB contributes to its ability to absorb and distribute mechanical shocks during a drop test. Thicker PCBs generally provide better shock absorption and impact resistance, helping to reduce the transmitted forces to the solder balls. However, there are certain limitations in increasing the thickness of PCB. Increasing the thickness of PCB could add cost, weight and thickness of the final product which could be less desirable. Hence, beyond a certain thickness limit, optimization must be performed using other design parameters like solder ball diameter, solder ball pitch. Considering the range from 1 mm to 1.5 mm for PCB thickness appears to be an optimal choice based on the analysis.

4.3.3. Solder ball diameter

As shown in Figure 15c, increasing the solder ball diameter from 0.075 mm to 0.9 mm demonstrates a strong inverse relationship with the peel stress. At diameters of 0.075 mm and 0.15 mm, the stress increases significantly, with percentage increase of 66.89% and 21.0% above the baseline value, respectively. However, as the solder ball diameter increases beyond 0.3 mm, the stress consistently decreases, with a 65.27% reduction observed at 0.9 mm. This stress reduction is due to the larger contact area provided by greater solder ball diameters, which enhances mechanical strength and, in turn, reduces induced stress during impact. The electrical requirements of the product will determine the necessary number of solder balls for the package. The dimensions of the package in turn dictates the pitch of BGAs. The diameter of the BGA is typically chosen to be 50–75% of pitch to prevent solder ball bridging during surface Mount Technology (SMT) process. Hence the BGA reliability is higher for larger diameter.

4.3.4. Solder ball pitch

The simulations conducted for solder ball pitches of 0.65 mm, 0.75 mm, 1 mm, 1.5 mm, 2.5 mm, 3 mm, and 4 mm reveal a non-linear, positive relationship with peel stress, as shown in Figure 15d. Peel stress increases rapidly at smaller pitches ranging from 0.65 to 1 mm, followed by a significant slowdown at larger pitches 2.5 to 3 mm, where it approaches a plateau. This behaviour underscores the importance of optimizing pitch size for both performance and cost efficiency. A smaller solder ball pitch allows for a greater number of solder joints in a given area, distributing the mechanical stress over a larger number of connections. Consequently, this enhances the ability of the device to absorb and distribute impact energy during drops. Hence it is evident that smaller pitch is effective in reducing the peel stress and increasing the reliability of solder joints.

4.3.5. Substrate modulus and thickness

Figures 15e and 15f show a gradual increase in peel stress as the substrate modulus and thickness increase from 0.25 to 3 times their baseline values. In both cases, the variation is moderate, with only a 10% decrease in peel stress observed at the extreme scales. Bending of the BGA package is proportional to the substrate modulus and substrate thickness. A stiffer package tends to transmit more mechanical stress to the solder joints upon impact during a drop test. This increased stress may lead to higher forces and strains on the joints, potentially affecting their integrity. Hence an increase in substrate modulus as well as substrate thickness leads to a decrease in the bending and hence increased stress.

4.3.6. Silicon thickness

Figure 15g indicates that the impact of silicon thickness on peel stress under drop loading is minimal or least significant. The stress value evaluated at the critical solder ball remained nearly constant despite variations in the thickness of the silicon from 0.25 to 3 times its baseline value which brought about only 5% variation in stress. It can be attributed to the fact that the higher modulus of the silicon chip compared to the PCB modulus causes less flexing thereby limiting the stress produced.

Figure 16 shows the peel stress variation with reference to percentage variation of PCBA geometrical and material properties, from which it is evident that among the analyzed parameters, solder ball pitch, PCB thickness, and solder ball diameter emerge as the most significant contributors to peeling stress. Solder ball pitch has a strong impact on stress especially at smaller scales where closer spacing reduces peeling stress. Similarly, varying PCB thickness shows significant stress reductions however thickness values of 1 mm–1.5 mm are considered optimal. Larger solder ball diameter also helps decrease peeling stress, thereby improving the reliable life of solder joints under drop impact. Moderate impacts are observed for PCB stiffness and substrate properties. In contrast, silicon thickness has the least impact, with minor variations in peeling stress across its scaling range. These insights highlight the need to prioritize solder ball pitch, PCB thickness, and solder ball diameter in the design process while balancing trade-offs in mechanical, electrical, and thermal performance.

Figure 16
% Variation of input parameters vs peel stress.

The results of drop tests could be utilized for assessing the quality of the model and enhancing confidence in the numerical outcomes. Additionally, employing an effective model can optimize PCBA design for drop impact loading, thereby improving the reliability of solder joints [¹, ⁵]. This research thoroughly investigates the impact of location of BGA on the PCB, drop orientation, and variations in geometrical and material properties of PCB assemblies under drop impact. Specifically, it examines the factors influencing induced stresses, consequently affecting solder joint failure. Shifting the BGA position from the center of the PCB to a 30 mm offset has led to a substantial 50% reduction in peeling stress. Different orientations upon impact can yield diverse stress patterns and impact points on the PCB surface. Consequently, the reliability of solder joints may be directly affected by the orientation of the board during mechanical stress events. Horizontal drops at 0° and 180° degrees are considered more vulnerable scenarios. A similar investigation by ZHOU et al. [¹³] experimentally, showed 0° orientation is most vulnerable orientation with maximum tensile plastic strain. The parametric analysis indicates that PCB modulus, PCB thickness, solder ball diameter, and solder ball pitch have a substantial impact on solder joint failure.

CHUNG and KWAK [¹¹] considering Ramberg-Osgood model for SAC305, WONG et al. [³²], using two step dynamic analysis, indicated that thinner PCBs deflect more, leading to shorter characteristic life. QU et al. [³³], in his research, utilizing the Darveaux model, indicated that a smaller pitch of solder joints results in optimal reliability during drop tests, as revealed by the strain energy density. In comparison, substrate modulus, thickness, and silicon thickness demonstrate relatively less significance in this regard. WONG et al. [³²] in his research stated that the amplification of stress is virtually independent of the package modulus or thickness.

5. CONCLUSIONS

This study investigates reliability of solder joints using Explicit dynamic analysis, focusing on solder joint stresses, strains, and board deformation. Results identify that solder balls on the board side are critical than BGA side with the corner-most solder balls nearer to board edges as the most vulnerable region, with maximum peel stress (162.12 MPa) and strain (0.001048). BGA Packages at the centre of the board face the highest failure risk, with stress significantly reduced by radial displacement (28.12 MPa at 7 × 7 mm and 82.92 MPa at 30 × 30 mm). Drop orientation also impacts reliability, with face-down drops generating the highest stress and vertical drops causing minimal stress (0.09 MPa).

Parametric analysis of PCBA highlights key factors affecting solder joint reliability.

• Increasing the PCB modulus and thickness contributes to a reduction in stress distribution in solder balls. Varying the PCB modulus from 30 GPa to 90 GPa reduces peeling stress by 25%, with stress reduction following a near-linear trend. A sharp decrease in peeling stress is observed as PCB thickness increases from 0.75 mm to 1 mm, followed by a more gradual reduction beyond 1 mm.

• The stress in solder balls is significantly influenced by both solder ball pitch and diameter. Increasing the diameter beyond 0.3 mm, reduced stress consistently, with a 65.27% reduction observed at 0.9 mm. Also, finer pitches ranging from 0.65–0.75 mm contributes to 25% stress reduction.

• Variations in substrate modulus and thickness contribute to stress variations, however their impact on stress levels is less significant compared to the influence of board properties, with only a 10% decrease in peel stress observed at extreme values.

• Variations in the thickness of silicon from 0.25 to 3 times its baseline value resulted in only a 5% variation in stress indicating that silicon thickness has a negligible impact on the stress distribution.

These findings emphasize the importance of optimizing PCB design parameters such as modulus, thickness, solder ball diameter, and pitch, as well as package positioning and drop orientation, to enhance solder joint reliability. This research offers valuable guidance for balancing performance, cost, and reliability in PCBA design.

Future research could explore the impact of underfill materials in drop tests through both experimental and simulation approaches. Additionally, experiments can be conducted to assess the material properties of multi-layered PCBs using three-point bending tests and strain rate-based tests.

6. BIBLIOGRAPHY

• ^[1] BAI, Y., NARDI, D.C., ZHOU, X., et al, “A new comprehensive model of damage for flexural subassemblies prone to fatigue”, Computers & Structures, v. 256, pp. 106639, 2021. doi: http://doi.org/10.1016/j.compstruc.2021.106639.
  » https://doi.org/10.1016/j.compstruc.2021.106639
• ^[2] ZHANG, P., XUE, S., WANG, J., “New challenges of miniaturization of electronic devices: electromigration and thermomigration in lead-free solder joints”, Materials & Design, v. 192, pp. 108726, 2020. doi: http://doi.org/10.1016/j.matdes.2020.108726.
  » https://doi.org/10.1016/j.matdes.2020.108726
• ^[3] SAMAVATIAN, V., MASOUMIAN, A., MAFI, M., et al, “Influence of directional random vibration on the fatigue life of solder joints in a power module”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, v. 9, n. 2, pp. 262–268, Feb. 2019. doi: http://doi.org/10.1109/TCPMT.2018.2838148.
  » https://doi.org/10.1109/TCPMT.2018.2838148
• ^[4] GU, J., LIN, J., LEI, Y., et al, “Experimental analysis of Sn-3.0Ag-0.5Cu solder joint board-level drop/vibration impact failure models after thermal/isothermal cycling”, Microelectronics and Reliability, v. 80, pp. 29–36, 2018. doi: http://doi.org/10.1016/j.microrel.2017.10.014.
  » https://doi.org/10.1016/j.microrel.2017.10.014
• ^[5] GLOBAL STANDARDS FOR THE MICROELECTRONICS INDUSTRY, JESD22-B111A Board level drop test method of components for handheld electronic products, Arlington, JEDEC, 2016.
• ^[6] MUTHURAM, N., SARAVANAN, S., “Free fall drop impact analysis of board level electronic packages”, Microelectronics Journal, v. 129, pp. 105601, 2022. doi: http://doi.org/10.1016/j.mejo.2022.105601.
  » https://doi.org/10.1016/j.mejo.2022.105601
• ^[7] LIU, F., MENG, G., ZHAO, M., et al, “Experimental and numerical analysis of BGA lead-free solder joint reliability under board-level drop impact”, Microelectronics and Reliability, v. 49, n. 1, pp. 79–85, 2009. doi: http://doi.org/10.1016/j.microrel.2008.10.014.
  » https://doi.org/10.1016/j.microrel.2008.10.014
• ^[8] ZHENG, T., AMINJIKARAI, B., YANG, M.A., “Finite element analysis of shock & vibration of a printed circuit board assembly using the beam elements to model the solder joints”, In: Proceedings of the IEEE 73rd Electronic Components and Technology Conference (ECTC), pp. 379–385, Orlando, FL, USA, 2023. doi: http://doi.org/10.1109/ECTC51909.2023.00070
• ^[9] WU, M.-L., LAN, J.-S., “Reliability and failure analysis of SAC 105 and SAC 1205N lead-free solder alloys during drop test events”, Microelectronics and Reliability, v. 80, pp. 213–222, 2018. doi: http://doi.org/10.1016/j.microrel.2017.12.013.
  » https://doi.org/10.1016/j.microrel.2017.12.013
• ^[10] LALL, P., PANCHAGADE, D., LIU, Y., et al, “Smeared-property models for shock-impact reliability of area-array packages”, Journal of Electronic Packaging, v. 129, n. 4, pp. 373–381, 2007. doi: http://doi.org/10.1115/1.2804085.
  » https://doi.org/10.1115/1.2804085
• ^[11] CHUNG, S., KWAK, J.B., “Comparative study on reliability and advanced numerical analysis of BGA subjected to product-level drop impact test for portable electronics”, Electronics, v. 9, n. 9, pp. 1515, 2020. doi: http://doi.org/10.3390/electronics9091515.
  » https://doi.org/10.3390/electronics9091515
• ^[12] YUAN, G., CHEN, X., SHU, X., “Failure analysis of the solder joints in flip-chip BGA packages under free-drop test”, Advanced Materials Research, v. 936, pp. 628–632, 2014. doi: http://doi.org/10.4028/www.scientific.net/AMR.936.628.
  » https://doi.org/10.4028/www.scientific.net/AMR.936.628
• ^[13] ZHOU, C.Y., YU, T.X., LEE, R.S.W., “Drop impact tests and analysis of typical portable electronic devices”, International Journal of Mechanical Sciences, v. 50, n. 5, pp. 905–917, 2008. doi: http://doi.org/10.1016/j.ijmecsci.2007.09.012.
  » https://doi.org/10.1016/j.ijmecsci.2007.09.012
• ^[14] BENDER, E., BERNSTEIN, J.B., BONING, D.S., “Modern trends in microelectronics packaging reliability testing”, Micromachines, v. 15, n. 3, pp. 398, 2024. doi: http://doi.org/10.3390/mi15030398. PubMed PMID: 38542645.
  » https://doi.org/10.3390/mi15030398
• ^[15] YUNUSA, V.A., “Reliability of solder joints in embedded packages using finite element methods”, M.Sc. Thesis, Portland State University, 2018.
• ^[16] WONG, E.H., MAI, Y.W., WOO, M., “Analytical solution for the damped-dynamics of printed circuit board and applied to study the effects of distorted half-sine support excitation”, IEEE Transactions on Advanced Packaging, v. 32, n. 2, pp. 536–545, 2009. doi: http://doi.org/10.1109/TADVP.2009.2014737.
  » https://doi.org/10.1109/TADVP.2009.2014737
• ^[17] LIU, L., XUE, S., NI, R., et al, “Board level drop test for evaluating the reliability of high-strength Sn-Bi composite solder pastes with thermosetting epoxy”, Crystals, v. 12, n. 7, pp. 924, 2022. doi: http://doi.org/10.3390/cryst12070924.
  » https://doi.org/10.3390/cryst12070924
• ^[18] FAN, X., RANOUTA, A.S., “Finite element modeling of system design and testing conditions for component solder ball reliability under impact”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, v. 2, n. 11, pp. 1802–1810, Nov. 2012. doi: http://doi.org/10.1109/TCPMT.2012.2204884.
  » https://doi.org/10.1109/TCPMT.2012.2204884
• ^[19] SHAO, J., ZHANG, H., CHEN, B., “Experimental study on the reliability of PBGA electronic packaging under shock loading”, Electronics, v. 8, n. 3, pp. 279, 2019. doi: http://doi.org/10.3390/electronics8030279.
  » https://doi.org/10.3390/electronics8030279
• ^[20] CHEN, Y., JING, B., LI, J., et al, “Failure analysis and modeling of solder joints in BGA packaged electronic chips”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, v. 11, n. 1, pp. 43–50, Jan. 2021. doi: http://doi.org/10.1109/TCPMT.2020.3040757.
  » https://doi.org/10.1109/TCPMT.2020.3040757
• ^[21] XIA, J., LI, G.Y., LI, B., et al, “Fatigue life prediction of Package-on-Package stacking assembly under random vibration loading”, Microelectronics and Reliability, v. 71, pp. 111–118, 2017. doi: http://doi.org/10.1016/j.microrel.2017.03.005.
  » https://doi.org/10.1016/j.microrel.2017.03.005
• ^[22] JING-EN, L., TONG, Y.T., XUEREN, Z., et al, “Solder joint failure modes, mechanisms, and life prediction models of IC packages under board level drop impact”, In: Proceedings of the 6th International Conference on Electronic Packaging Technology, pp. 382–388, Shenzhen, China, 2005. doi: http://doi.org/10.1109/ICEPT.2005.1564714.
• ^[23] CHOI, N.-Y., ZHANG, S.-U., “Terminal strength test of TO-220 packaged Schottky barrier diode using finite element method”, Microelectronics and Reliability, v. 151, pp. 115235, 2023. doi: http://doi.org/10.1016/j.microrel.2023.115235.
  » https://doi.org/10.1016/j.microrel.2023.115235
• ^[24] DEPIVER, J.A., MALLIK, S., HARMANTO, D., et al, “Creep damage of BGA solder interconnects subjected to thermal cycling and isothermal ageing”, In: Proceedings of the IEEE 21st Electronics Packaging Technology Conference (EPTC), pp. 143–153, Singapore, 2019. doi: http://doi.org/10.1109/EPTC47984.2019.9026710.
• ^[25] WANG, P., LEE, Y.C., LEE, C., et al, “Solder joint reliability assessment and pad size studies of FO-WLP with glass substrate”, IEEE Transactions on Device and Materials Reliability, v. 21, n. 1, pp. 96–101, Mar. 2021. doi: http://doi.org/10.1109/TDMR.2021.3056054.
  » https://doi.org/10.1109/TDMR.2021.3056054
• ^[26] YUAN, C., DE JONG, S.D.M., DRIEL, W.D.V., “AI-assisted design for reliability: review and perspectives”, In: Proceedings of the 25th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), pp. 1–12, Catania, Italy, 2024. doi: http://doi.org/10.1109/EuroSimE60745.2024.10491447.
• ^[27] MAO, M., WANG, W., LU, C., et al, “Machine learning for board-level drop response of BGA packaging structure”, Microelectronics and Reliability, v. 134, pp. 114553, 2022. doi: http://doi.org/10.1016/j.microrel.2022.114553.
  » https://doi.org/10.1016/j.microrel.2022.114553
• ^[28] CHEN, K., ZHANG, Y., CHENG, G., et al, “A machine learning and finite element simulation based void inspection for higher solder joint reliability”, Microelectronics and Reliability, v. 154, pp. 115323, 2024. doi: http://doi.org/10.1016/j.microrel.2024.115323.
  » https://doi.org/10.1016/j.microrel.2024.115323
• ^[29] KAMARAJ, L., SHARMA, P., SHINDE, S.S., et al, “Effect of zirconium diboride on microstructural and mechanical properties of AA2017 produced via liquid stir casting”, Matéria, v. 29, n. 4, e20240463, 2024. doi: http://doi.org/10.1590/1517-7076-rmat-2024-0411.
  » https://doi.org/10.1590/1517-7076-rmat-2024-0411
• ^[30] ABAQUS, ABAQUS user Manual (version 6.5), ABAQUS, Inc., 2005.
• ^[31] JUNTUNEN, E., SITOMANIEMI, A., TAPANINEN, O., et al, “Thermal performance comparison of thick-film insulated aluminum substrates with metal core pcbs for high-power LED modules”, IEEE Transactions on Components, Packaging, and Manufacturing Technology, v. 2, n. 12, pp. 1957–1964, 2012. doi: http://doi.org/10.1109/TCPMT.2012.2206390.
  » https://doi.org/10.1109/TCPMT.2012.2206390
• ^[32] WONG, E.H., MAI, Y.W., SEAH, S.K.W., “Board level drop impact fundamental and parametric analysis”, Journal of Electronic Packaging, v. 127, n. 4, pp. 496–502, 2005. doi: http://doi.org/10.1115/1.2065747.
  » https://doi.org/10.1115/1.2065747
• ^[33] QU, X., CHEN, Z., QI, B., et al, “Board level drop test and simulation of leaded and lead-free BGA-PCB Assembly”, Microelectronics and Reliability, v. 47, n. 12, pp. 2197–2204, 2007. doi: http://doi.org/10.1016/j.microrel.2006.10.017.
  » https://doi.org/10.1016/j.microrel.2006.10.017

Publication Dates

• Publication in this collection
  10 Feb 2025
• Date of issue
  2025

History

• Received
  15 Nov 2024
• Accepted
  27 Dec 2024