A Balanced-to-Single-Ended Wilkinson Power Divider

Abstract

A balanced-to-single-ended (BTSE) Wilkinson power divider of planar microstrip structure is proposed in this paper. It has a balanced input and two single-ended outputs. Cascade of a balun and a conventional power divider can be replaced by this proposed structure. Based on the theory of mixed-mode S parameters and the admittance matrix method, the critical parameters are determined. The four-port network is analyzed by simplifying it to two-port network with other ports matched at the central frequency. Then the key parameters are derived and the impact of a freely selected variable on the bandwidth is also discussed. An example of 2.4GHz BTSE power divider is designed. The simulated and measured results show the effectiveness of the method: differential-mode transmissions are better than −3.25dB, common-mode transmissions are lower than −28.6dB, common-mode return loss is −0.10dB, differential-mode return loss and isolation is lower than −23.7dB. While the operating bandwidth is 20%.

Index Terms
balanced circuit; power divider; mixed-mode S-matrix

I. Introduction

Balanced RF circuits have more advantages than single-ended ones. The most important advantage is the ability of anti common-mode interference. As power divider is an important microwave/millimeter wave passive device, scholars have made a deep research on balanced power dividers [¹–⁷]. In [¹], a wide band miniature balanced power divider is designed with the coupled lines. Then a balanced Wilkinson power divider with microstrip structure was presented [²], it contains four lumped resistors which affect the performance when working at high frequency. Later, some scholars improved the structure by using two resistors [³]. Further in [⁴], the lumped resistors were reduced to one. By using half-mode substrate integrated waveguide (SIW) structure, a balanced symmetric Gysel power divider is designed [⁵]. Also, balanced Gysel power divider with arbitrary power division ratio [⁶] and dual-band balanced Wilkinson power divider [⁷] are designed.

As mentioned above, these studies are all about the balanced-to-balanced (BTB) power divider, but in some modern practical applications, it may demand a power divider which contains both single-ended port and balanced port, such as when the signals received by a balanced antenna need to be processed by single-ended receivers [⁸] or when the differential power amplifier need to be connected to a single-ended antennas to work in a radar system effectively [⁹]. Research in this area is relatively few. A BTSE power divider is designed with double-side structure [¹⁰], which brings inconvenience to practical application. [¹¹] proposed a BTSE power divider with filtering function, however, the operating bandwidth of it is less than 7%.

In this paper, the relationship between mixed-mode S-matrix and traditional S-matrix of the four port network of the proposed power divider is analyzed and derived, then a transformation is introduced to simplify the design process. At last, based on the mixed-mode S parameters theory and the admittance matrix method of the two-port balanced network, a new BTSE power divider with planar microstrip structure is proposed. And its performances are demonstrated by the simulated and measured results. The impact of a freely selected variable on the bandwidth is also discussed.

II. Analysis and Derivation of Key Parameters

As shown in Fig. 1, a three port BTSE power divider transmit the input signal from balanced port 1 to single-ended ports 2 and 3. In the research of balanced circuit, we often use mixed-mode S-matrix to replace the traditional S-matrix. Its mixed-mode S-matrix is

Fig. 1
Schematic diagram of a three port BTSE power divider

(1) $$\left[S_M\right]=\left[\begin{array}{llll}{S}_{DD11}\hfill & S_{DC11}\hfill & S_{DS12}\hfill & S_{DS13}\hfill \\ S_{CD11}\hfill & S_{CC11}\hfill & S_{CS12}\hfill & S_{CS13}\hfill \\ S_{SD21}\hfill & S_{SC21}\hfill & S_{SS22}\hfill & S_{SS23}\hfill \\ S_{SD31}\hfill & S_{SC31}\hfill & S_{SS32}\hfill & S_{SS33}\hfill \end{array}\right]=\left[\begin{array}{lll}{S}_{DD}\hfill & S_{DC}\hfill & S_{DS}\hfill \\ S_{CD}\hfill & S_{CC}\hfill & S_{CS}\hfill \\ S_{SD}\hfill & S_{SC}\hfill & S_{SS}\hfill \end{array}\right]$$

In this matrix, ${}^{S_{XYij}}$ means the S-parameter when port j is in Y mode excitation and port i is in X mode response, where X, Y are corresponding to differential mode (D), common mode (C) or single-ended mode (S), while i, j are corresponding to port 1, port 2 or 3. At the same time, ${}^{S_{XY}}$ represents the corresponding matrix block.

Typically, the parameters should meet the following conditions:

1. The power divider should be reciprocal, so its mixed-mode S-matrix is symmetric ${(}^{S_{XYij}=S_{YXji}})$;

2. Each port should be matched to the differential signal, at the same time, single ports are also matched ${(}^{S_{DDii}=0}\text{and}{}^{S_{SSii}=0})$;

3. The input common mode noise should be fully reflected, with no mutual conversion between the common mode signal and differential mode signal ${(}^{\left|S_{CCii}\right|=1}{\text{and}}^{\left|S_{CDii}\right|=\left|S_{DCii}\right|=\left|S_{CDij}\right|=\left|S_{DCij}\right|=0})$;

4. The output ports should be isolated from each other ${(}^{\left|S_{SS23}\right|=0}{\text{and}}^{\left|S_{SS32}\right|=0})$.

According to these, the desired mixed-mode S-matrix of the power divider with equal power division will be:

(2) $$\left[S_M\right]=\left[\begin{array}{cccc}0& 0& \sqrt{2}{e}^{-j{\phi }_1}/2& \sqrt{2}{e}^{-j{\phi }_2}/2\\ 0& e^{-j{\phi }_3}& 0& 0\\ \sqrt{2}{e}^{-j{\phi }_1}/2& 0& 0& 0\\ \sqrt{2}{e}^{-j{\phi }_2}/2& 0& 0& 0\end{array}\right]$$

where ^φ₁, ^φ₂, ^φ₃ are the phase shift of the S-parameters. To the BTSE power divider in this paper, ^φ₁, ^φ₂, ^φ₃ are set to ^{φ₁ = π/2}, ^{φ₂ = -π/2}, ^{φ₁ = π}. So we can get the mixed-mode S-matrix:

(3) $$\left[S_M\right]=\left[\begin{array}{cccc}0& 0& -\frac{\sqrt{2}}{2}j& \frac{\sqrt{2}}{2}j\\ 0& -1& 0& 0\\ -\frac{\sqrt{2}}{2}j& 0& 0& 0\\ \frac{\sqrt{2}}{2}j& 0& 0& 0\end{array}\right]$$

In order to get the traditional S-matrix to derive the key design parameters, we need to know the transformation between mixed-mode S-matrix and traditional S-matrix. To simplify the calculation, we rearrange the traditional S-matrix: Supposing a network containing N balanced ports and M single ports, the traditional S-matrix is rearranged as this block matrix:

(4) $$\left[S\right]=\left[\begin{array}{ccc}{\left[S_{aa}\right]}_{M\times M}& {\left[S_{ab}\right]}_{M\times N}& {\left[S_{ac}\right]}_{M\times N}\\ {\left[S_{ba}\right]}_{N\times M}& {\left[S_{bb}\right]}_{N\times N}& {\left[S_{bc}\right]}_{N\times N}\\ {\left[S_{ca}\right]}_{N\times M}& {\left[S_{cb}\right]}_{N\times N}& {\left[S_{cc}\right]}_{N\times N}\end{array}\right]$$

where a, b, c respectively represents the single-ended port, the positive end of the balanced port and the negative end of the balanced port.

Based on these and derivation of the relationship between mixed-mode S-matrix and traditional S-matrix in [¹²], we can get:

(5) $$\left[S\right]=\frac{1}{2}\times \left[\begin{array}{ccc}2S_{SS}& \sqrt{2}\left(S_{SD}+S_{SC}\right)& \sqrt{2}\left(-S_{SD}+S_{SC}\right)\\ \sqrt{2}\left(S_{DS}+S_{CS}\right)& S_{DD}+S_{CD}+S_{DC}+S_{CC}& -S_{DD}-S_{CD}+S_{DC}+S_{CC}\\ \sqrt{2}\left(-S_{DS}+S_{CS}\right)& -S_{DD}+S_{CD}-S_{DC}+S_{CC}& S_{DD}-S_{CD}-S_{DC}+S_{CC}\end{array}\right]$$

So we can get the traditional S-matrix to the BTSE power divider in this paper:

(6) $$\left[S\right]=\left[\begin{array}{cccc}{S}_{22}& S_{23}& S_{1+2}& S_{1+3}\\ S_{32}& S_{33}& S_{1-2}& S_{1-3}\\ S_{21+}& S_{21-}& S_{1+1+}& S_{1+1-}\\ S_{31+}& S_{31-}& S_{1-1+}& S_{1-1-}\end{array}\right]=\left[\begin{array}{cccc}0& 0& -\frac{1}{2}j& \frac{1}{2}j\\ 0& 0& \frac{1}{2}j& -\frac{1}{2}j\\ -\frac{1}{2}j& \frac{1}{2}j& -\frac{1}{2}& -\frac{1}{2}\\ \frac{1}{2}j& -\frac{1}{2}j& -\frac{1}{2}& -\frac{1}{2}\end{array}\right]$$

According to the constraint conditions, the four-port S-parameters of the BTSE power divider are derived. The BTSE power divider can be built up with the structure shown in Fig. 2:

Fig. 2
Structure of the BTSE power divider

As shown in Fig. 2, this BTSE Wilkinson power divider consists of four transmission lines and a resistance with the electrical lengths of the transmission lines are ^{θ₁ = θ₂ = π/2} and ^{θ₃ = θ₄ = π}. While Z1, Z2, Z3, Z4 and R1 are to be determined. All the four ports have the same port impedance of ^{Z₀ = 50Ω}.

In order to determine the critical parameters, the structure is analyzed by simplifying it to two-port network with other ports matched at the central frequency. As shown in Fig. 3,

Fig. 3
Network between 2 and 3:(a) The equivalent network between port 2 and 3;(b) The circuit represented by Y_L;(c) The circuit represented by Y_M

using (6) we get:

(7) $${\left[S\right]}_{23}=\left[\begin{array}{cc}{S}_{22}& S_{23}\\ S_{32}& S_{33}\end{array}\right]=\left[\begin{array}{cc}0& 0\\ 0& 0\end{array}\right]$$

According to (7) and the relationship between S-matrix and admittance matrix, we have:

(8) $${\left[Y\right]}_{23}=\left[\begin{array}{cc}{Y}_0& 0\\ 0& Y_0\end{array}\right]$$

where ^{Y₀ = 1/50Ω-1} is the admittance of each port. The admittance matrix of the network can also be expressed as:

(9) $${\left[Y\right]}_{23}={\left[Y\right]}_L+{\left[Y\right]}_M$$

Based on Fig. 3 (b) and (c) we can get theirs ABCD matrix:

(10a) $${\left[ABCD\right]}_L=\left[\begin{array}{cc}0& j{Z}_1\\ j{Y}_1& 0\end{array}\right]\left[\begin{array}{cc}1& 0\\ Y_0& 1\end{array}\right]\left[\begin{array}{cc}-1& 0\\ 0& -1\end{array}\right]\left[\begin{array}{cc}1& 0\\ Y_0& 1\end{array}\right]\left[\begin{array}{cc}0& j{Z}_2\\ j{Y}_2& 0\end{array}\right]=\left[\begin{array}{cc}\frac{Z_1}{Z_2}& 2Z_1{Z}_2{Y}_0\\ 0& \frac{Z_2}{Z_1}\end{array}\right]$$

(10b) $${\left[ABCD\right]}_M=\left[\begin{array}{cc}-1& 0\\ 0& -1\end{array}\right]\left[\begin{array}{cc}1& R_1\\ 0& 1\end{array}\right]=\left[\begin{array}{cc}-1& -R_1\\ 0& -1\end{array}\right]$$

According to (10) and the relationship between ABCD-matrix and admittance matrix, we get:

(11a) $${\left[Y\right]}_L=\left[\begin{array}{cc}\frac{1}{2Z_1^2{Y}_0}& -\frac{1}{2Z_1{Z}_2{Y}_0}\\ -\frac{1}{2Z_1{Z}_2{Y}_0}& \frac{1}{2Z_2^2{Y}_0}\end{array}\right]$$

(11b) $${\left[Y\right]}_M=\left[\begin{array}{cc}\frac{1}{R_1}& \frac{1}{R_1}\\ \frac{1}{R_1}& \frac{1}{R_1}\end{array}\right]$$

Based on the comparison of (8), (9) and (11), we have:

(12) $$\{\begin{array}{c}\frac{1}{2Z_1^2{Y}_0}+\frac{1}{R_1}=\frac{1}{2Z_2^2{Y}_0}+\frac{1}{R_1}=Y_0\\ -\frac{1}{2Z_1{Z}_2{Y}_0}+\frac{1}{R_1}=0\end{array}$$

The solution of this equation system is ^{Z₁ = Z₂ = Z₀} and ^{R₁ = 2Z₀} where ^{Z₀ = 1/Y₀}.

From the above results, we can know that Z₃ and Z₄ can be freely selected. In this paper, we set Z₃ = Z₄ =Z_x at central frequency. Next, the impact of the freely selected variable Zx on the relative bandwidth (BW) of the power divider will be introduced.

From the above discussion, we can know that the parameters in the matrix blocks ^{S_SS, S_CS, S_DD} (isolation, common-mode rejection, and differential-mode return loss) mainly determine the performance of the power divider. We define the minimum relative bandwidth of these parameters as the relative bandwidth of the power divider. Fig. 4 presents the Zx in the range of (20Ω< ZX <200Ω), with the relative bandwidth with the trend of Zx change. It can be seen when the Zx is equal to 60Ω, the power divider get the maximum relative bandwidth of 27.5%. We take Z_x = 50Ω as an example to realize and test the proposed power divider.

Fig. 4
Relationship Between Z_x and the relative bandwidth

III. Realization of BTSE Power Divider

According to the above analysis and design, a balanced-to-single-ended power divider is realized, as shown in Fig. 5. It is fabricated on a 0.508-mm-thick Rogers4003 substrate, with ε_r = 3.55 and tan δ = 0.0027. The operating band is centered at f₀ = 2.4GHz. The positive and negative terminals of the balanced input port 1 are located on the left, while the two single-ended outputs are on the right. The geometric parameters in Fig. 5 are L=12 mm, L1=18.5 mm, L2=37 mm, L3=12 mm, W1=1.13 mm, W2=1.13 mm, W3=1.13 mm, g=1.2 mm.

Fig. 5
Photo of the BTSE power divider

Finally, the simulated results and measured results obtained by Ansoft HFSS and Aglient E5071 are all shown in Fig. 6.

Fig. 6
Simulated and measured results of the BTSE power divider prototype:(a) Parameters of balanced port 1;(b) Differential mode transmission parameters S_ds;(c) Common mode transmission parameters |S_cs|;(d) Return loss and isolation of ports 2 and 3

As we can see, good performances have been successfully achieved with the proposed BTSE power divider. At center frequency 2.4GHz, the measured differential-mode transmissions are: |Sds12|=-3.25dB, |Sds13|=-3.17 dB; common-mode transmission parameters |Scs12|, |Scs13| are respectively −30.5dB and −28.6dB; differential-mode return loss of port 1 is |Sdd11|=-25.1 dB while common-mode return loss is |Scc11|=-0.10dB; the return loss of ports 2 and 3 are |Sss22|=-22.3dB, |Sss33|=-32.4dB; isolation parameters between 2 and 3(|Sss23|)is −23.7dB. The common-mode transmissions, the differential-mode return loss, the return loss of ports 2 and 3, the isolation between 2 and 3 are all lower than −15dB between 2.16 GHz~2.61 GHz. The relative bandwidth is 20%. Due to the error of the device fabrication and parameter testing, the experimental results and the simulated results have some differences in some parameters (Sdc11 and Sss33). Except this, the simulated results and the experimental results are in good agreement.

IV. Conclusion

Balanced-to-single-ended power divider makes up for the lack of performance when connect balanced devices and single-ended devices in many systems, and the research of this power divider is particularly important. A BTSE Wilkinson power divider of planar microstrip structure is proposed, investigated, and fabricated in this paper based on the theory of mixed-mode S parameters and the admittance matrix method. At center frequency 2.4GHz, differential-mode transmissions are|Sds12|=-3.25dB, |Sds13|=-3.17 dB, common-mode transmissions|Scs12|, |Scs13|are respectively −30.5dB and −28.6dB, common-mode return loss|Scc11|is −0.10dB, differential-mode return loss is|Sdd11|=-25.1 dB, isolation|Sss23|is −23.7dB. The 15dB relative bandwidth is about 20%. The simulated and measured results show its great merits of low insertion loss, good return loss, high isolation and high common-mode rejection (common-mode transmissions). Therefore, power divider designed in this paper can meet the requirements of most radar and communication systems.

Acknowledgment

This work is supported by Foundation of Zhejiang Province Key Laboratory of Automobile Safety and Opening Foundation of Jiangsu Key Laboratory of Spectral Imaging and Intelligent Sense.

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Publication Dates

• Publication in this collection
  Sept 2017

History

• Received
  14 Feb 2017
• Reviewed
  16 Feb 2017
• Accepted
  04 Aug 2017