A JL-SDR-IMPATT Device with Improved Efficiency

Abstract

An attempt has been made to present a new device which will function as a highly efficient SDR (Single Drift Region) P+-N- N+ IMPATT diode utilizing the advantages of a junctionless field effect transistor. The basic idea is to convert a uniform N+ region into a (P+-N-N+) structure without any requirement of physical doping. As the present device works on the principle of a junctionless channel, variability and short channel effects are significantly reduced as compared to the conventional TFET though the requirement of an extra gate increases a few fabrication steps. Further, efficiency more than conventional SDR IMPATT diode is achievable without any physical doping.

Index Terms
ControlGate; efficiency; electric field; IMPATT; P-gate; SDR

I. INTRODUCTION

The IMPATT (IMPact-Avalanche-Transit Time) diode is a popular transit time device which gains its reputation in microwave (3-30 GHz) and millimeter wave (30-300 GHz) digital and analog communication systems as well as in radar for civilian purposes and for defense systems in missiles. In order to produce negative resistance at microwave frequencies, these diodes utilize impact ionization and transit time properties of semiconductor structures. Impact ionization is a process of formation of additional holes and electrons by knocking them out of the crystal structure due to high electrons and holes velocity. In IMPATT devices, negative resistances arise from two delays (avalanche delay-caused by finite build-up time of avalanche current, transit time delay- caused by the finite time taken by the carriers to cross the drift region) which cause the current to lag behind voltage [¹]. These two delays add up to 180° phase lag at a particular frequency and so the diode resistance is negative corresponding to that frequency.

On the other hand, it is observed that the characteristics of a nano-scale Metal Oxide Semiconductor Field Effect Transistors (MOSFET) have deteriorated owing to continual down scaling in size. Due to continual reduction in the dimensions of the MOS devices, various short channel effects (SCEs) such as Drain Induced Barrier Lowering(DIBL), gate tunneling, punch through, surface scattering etc are very much predominant along with several severe fabrication issues (especially in the sub-20nm channel region). So continuous efforts have been made in the recent years to improve the SCE immunity by using single as well as dual material double gate SOI/SON MOSFET structures [²-⁵]. However, these severe issues especially that of fabrications have been reduced by junctionless tunnel Field effect Transistor (absence of physical p-n junction in the source or drain side) where only a uniformly doped channel has been present [⁶-¹¹]. This structure produces excellent immunity to SCEs (Short Channel Effects) and double-gate or multi-gate devices offer better scalability options. Besides, this device is simpler to fabricate and has less variability and better electrical properties than MOSFET. So, these attractive advantages of the junctionless TFETs encourage us to use this kind of devices as junctionless SDR IMPATT device.

At different millimeter-wave window frequencies, Si and GaAs IMPATTs are already established as efficient and powerful sources [¹²-¹⁴]. For generation of RF power at THz frequencies, the potentiality of wide band-gap materials (GaN, SiC) has been reported in the recent years. Though different semiconductor materials like GaAs, InP, GaN have been used for IMPATT development to achieve higher efficiency, power output and frequency range, silicon still remains the most reliable material for millimeter-wave IMPATTs owing to its advanced technology and stability. The device efficiency of a silicon SDR (p+-n-n+) IMPATT diode at Ka-band is found to be 7.84%-8.98%. The maximum efficiency observed for 4H-SiC SDR IMPATT diodes is 23.28% (for Ka band) [¹⁵-¹⁷]. Since this efficiency is quite low, continuous efforts have been made in the recent years to increase the efficiency.

In this paper, an attempt has been made to present a new device which will function as a highly efficient SDR (Single Drift Region) P+-N-N+ IMPATT diode utilizing the concept of a junctionless field effect transistor. The basic idea is to convert a uniform N+ region into a (P+-N-N+) structure without any requirement of physical doping. Since this device is based on the principle of a junctionless channel, variability and short channel effects immunity improves as compared to the conventional TFET though the requirement of an extra gate increases a few fabrication steps. Besides without any physical doping greater efficiency can be achieved than that of a normal SDR IMPATT diode.

II. DEVICE DESCRIPTION

The proposed device structure is a lateral n+-type JLFET which uses two isolated gates (Control Gate and P-gate) of two different metal work functions, to make the layer beneath the gates n-type and p+- type. We have chosen the metal work function as 4.27 eV and 5.93eV for the CG and PG electrode, to make the layer beneath the CG and the PG electrode n-type and p+-type respectively [¹⁸-¹⁹]. As soon as the contact is made between metal oxide and the N+ semiconductor, the electrons will flow from the semiconductor to the metal and thus Fermi level goes down and in equilibrium this level is aligned with the Fermi level of the metal. For higher metal work function, more and more electron flow from the semiconductor to the metal and the Fermi level goes down more towards the valence band. In this way, a N+ region can be converted to N and P+ region depending on the metal work function. The CG and PG are both kept at zero bias.

Fig.1
The device structure indicating the N+, N and P+ regions along with the Control gate and P gate where two different metals(indicated by blue and green) and oxide layers(indicated by yellow).

Fig.2
The approximate energy band diagram for the N+, N and P+ regions

III. ANALYTICAL MODEL OF ELECTRIC FIELD AND EFFICIENCY

Considering n+ degenerate type semiconductor bar, the position of the Fermi level for this degenerate semiconductor can be written as [²⁰]

(1) $$E_{Fn+}=E_c+kT[\mathit{ln}(\frac{n_{n+}}{N_c})+{\mathit{2}}^{-\frac{\mathit{3}}{\mathit{2}}}\mathit{(}\frac{n_{n+}}{N_c}\mathit{)}\mathit{]}$$

where N_c is the carrier density in the conduction band, k is the Boltzmann's constant, T is the temperature in Kelvin, n_n+ is the carrier concentration in the n+ bar and E_c is the conduction band energy

The position of the Fermi level for a n- type region can be written as

(2) $$E_{Fn-}=E_c+kT\mathit{[}\mathit{\text{ln}}\mathit{(}\frac{n_{n-}}{N_c}\mathit{)}\mathit{]}$$

where n_n- -the carrier concentration in the n region Solving equations (1) and (2) we get,

(3) $$E_{Fn-}=E_{Fn+}+kT\mathit{[}\mathit{ln}\mathit{(}\frac{n_{n-}}{n_{n+}}\mathit{)}-{\mathit{2}}^{-\frac{\mathit{3}}{\mathit{2}}}\mathit{(}\frac{n_{n+}}{N_c}\mathit{)}\mathit{]}$$

Again, the position of the Fermi level for a p+ degenerate type region can be written as

(4) $$E_{F_{p+}}=E_v-kT\mathit{[}\mathit{ln}\mathit{(}\frac{p_{p+}}{N_v}\mathit{)}+{\mathit{2}}^{-\frac{\mathit{3}}{\mathit{2}}}\mathit{(}\frac{p_{p+}}{N_v}\mathit{)}\mathit{]}$$

where p_p+ is the concentration of the p+ region and N_v is the carrier density in the valence band Now, solving equations (1) and (4) we get

(5) $$E_{F_{p+}}=E_{Fn+}-E_g-kT\mathit{[}\mathit{ln}\mathit{(}\frac{p_{p+}{n}_{n+}}{N_c{N}_v}\mathit{)}-{\mathit{2}}^{-\frac{\mathit{3}}{\mathit{2}}}\mathit{(}\frac{n_{n+}}{N_c}+\frac{p_{p+}}{N_v}\mathit{)}\mathit{]}$$

The metal work functions for the Control gate and the P-gate can be expressed as

(6) $${\varphi }_{MC}={\varphi }_{sn+}+\mathit{(}\frac{E_{Fn+}-E_{Fn-}}{q}\mathit{)}$$

(7) $${\varphi }_{MP}={\varphi }_{sn+}+\mathit{(}\frac{E_{Fn+}-E_{Fp+}}{q}\mathit{)}$$

where ϕ_MC ϕ_MP -the metal work functions for the Control Gate and the P-gate and ϕ_sn+ -the semiconductor work function

Solving the above equations we get,

(8) $${\varphi }_{MC}={\varphi }_{MP}+\mathit{(}\frac{E_{Fp+}-E_{Fn-}}{q}\mathit{)}$$

The conditions for converting the N+ region to intrinsic-type, n-type and p+-regions are $\Delta E_{min}=\frac{E_g}{2}-3kT,\Delta E<\Delta E_{min},E_g-6kT>\Delta E>\Delta E_{min}$ and $\Delta E>E_g-6kT$

Now, from the 2D-Poisson's equation, the electrostatic potential profile can be written as

(9) $$\frac{{\partial }^2\psi }{\partial x^2}+\frac{{\partial }^2\psi }{\partial y^2}=\frac{q{N}_D}{{\epsilon }_{si}}$$

where N_D is the donor concentration in the n region of the device, q is the electronic charge and ε_si is the silicon substrate permittivity.

An approximate solution of the 2D potential distribution can be proposed assuming a parabolic potential as suggested by Young [²¹]

(10) $$\psi \mathit{(}x,y\mathit{)}={\psi }_s\mathit{(}x\mathit{)}+a_1\mathit{(}x\mathit{)}y+a_2\mathit{(}x\mathit{)}{y}^2$$

whereψ_s(x) -the surface potential which varies along the channel a₁, a₂ are functions of x. Now. introduction of symmetric conditions with respect to $\frac{t_{si}}{2}$ [²²] leads to

(11) $$\psi \mathit{(}x,y\mathit{)}={\psi }_s\mathit{(}x\mathit{)}+a_1\mathit{(}x\mathit{)}y-\frac{a_1\mathit{(}x\mathit{)}{y}^2}{t_{si}}$$

where t_si -the substrate thickness

With the introduction of boundary conditions at the surface i. e. ${\frac{\partial \psi \mathit{(}x,y\mathit{)}}{\partial y}|}_{y=0}=\frac{{\epsilon }_{ox}}{{\epsilon }_{si}}\frac{\mathit{(}{\psi }_s\mathit{(}x\mathit{)}-V_{gp{+}^i}\mathit{)}}{t_{ox}}$, we then derived an expression for a₁ (x)

(12) $${\frac{\partial \psi \mathit{(}x,y\mathit{)}}{\partial y}|}_{y=0}=a_1\mathit{(}x\mathit{)}=\frac{{\epsilon }_{ox}}{{\epsilon }_{si}}\frac{\mathit{(}{\psi }_s\mathit{(}x\mathit{)}-V_{gp{+}^i}\mathit{)}}{t_{ox}}$$

where $V_{gp{+}^i}=V_{gp+}-{\varphi }_{MS}$ and t_ox-the oxide thickness

Substituting the value of a₁ (x) from equation (12) to (11) we get,

(13) $$\psi \mathit{(}x,y\mathit{)}={\psi }_s\mathit{(}x\mathit{)}\mathit{[}\mathit{1}+\frac{{\epsilon }_{ox}}{{\epsilon }_{si}}\frac{y}{t_{ox}}-\frac{{\epsilon }_{ox}}{{\epsilon }_{si}}\frac{y^2}{t_{ox}{t}_{si}}\mathit{]}+\frac{{\epsilon }_{ox}}{{\epsilon }_{si}}\frac{V_{gp{+}^i}}{t_{ox}}\mathit{[}\frac{y}{t_{si}}-\mathit{1}\mathit{]}$$

Now, substituting the above expression of ψ(x, y) in (9), a new differential equation in terms of the surface potential is obtained as

(14) $$\frac{{\partial }^2{\psi }_s}{\partial x^2}-\frac{2{\epsilon }_{ox}{\psi }_s\mathit{(}x\mathit{)}}{{\epsilon }_{si}{t}_{ox}{t}_{si}}+\frac{2{\epsilon }_{ox}{V}_{gp{+}^i}}{{\epsilon }_{si}{t}_{ox}{t}_{si}}=\frac{q{N}_D}{{\epsilon }_{si}}$$

Let $M=\frac{2{\epsilon }_{ox}}{{\epsilon }_{si}{t}_{ox}{t}_{si}}$, $P=\frac{q{N}_D}{{\epsilon }_{si}}-M{V}_{gp{+}^i}$

Therefore, the equation (14) simplifies to

(15) $$\frac{{\partial }^2{\psi }_s\mathit{(}x\mathit{)}}{\partial x^2}-M{\psi }_s\mathit{(}x\mathit{)}=P$$

Solving the differential equation of (7) we get

(16) $${\psi }_s\mathit{(}x\mathit{)}=A{e}^{\delta x}+B{e}^{-\delta x}-\frac{P}{M}$$

where $\delta =\sqrt{M}$

Now, the boundary conditions-

${\psi }_s\mathit{(}0,0\mathit{)}={\psi }_s\mathit{(}0,t_{si}\mathit{)}=V_{bi},{\psi }_s\mathit{(}L,0\mathit{)}={\psi }_s\mathit{(}L,t_{si}\mathit{)}=V_{bi}+V_{n+p+}$ have been used to solve for the constants A and B

$$\begin{array}{l}B=\frac{\mathit{(}{V}_{bi}+\frac{P}{M}\mathit{)}{e}^{\delta L}-\mathit{(}{V}_{bi}+V_{n+p+}+\frac{P}{M}\mathit{)}}{e^{\delta L}-e^{-\delta L}}\\ =\mathit{(}\frac{e^{\delta L}}{e^{\delta L}-e^{-\delta L}}\mathit{)}\mathit{[}\mathit{(}{V}_{bi}+\frac{P}{M}\mathit{)}-\mathit{(}{V}_{bi}+V_{n+p+}+\frac{P}{M}\mathit{)}{e}^{-\delta L}\mathit{]}\\ A=V_{bi}+\frac{P}{M}-B\end{array}$$

where V_n+p+ -the applied voltage across the p+ and n+ regions, V_bi - built-in potential

Now the expression of electric field can be obtained from differentiating the equation (16),

(17) $$E_s\mathit{(}x\mathit{)}=\delta \mathit{[}A{e}^{\delta x}-B{e}^{-\delta x}\mathit{]}$$

Now, if an ac voltage v = V_max sin wt is superimposed on applied dc voltage V_r = V_n+p+, the efficiency of the device is given by [²³]

(18) $$Efficiency\mathit{(}\eta \mathit{)}=\frac{2V_{max}}{\pi V_B}$$

where V_B is the breakdown voltage and is given by

(19) $$V_B=x_A{\xi }_A+\mathit{(}W-x_A\mathit{)}{\xi }_D$$

where ξ _A, ξ _D are electric field in the avalanche and the drift region and x_A, W are the avalanche width and depletion width where the electric field decays to zero.

The maximum ac voltage depends on swing in the electric field Δξ in the avalanche and drift region $V_{max}=\Delta \xi W$

Considering optimistic situation i. e. the voltage across the drift zone swings to zero thereby making the electric field zero at the maximum negative voltage of the ac voltage i. e. $\Delta \xi ={\xi }_D$ and the with the assumption that ${\xi }_A=2{\xi }_D$, the efficiency can be modified as [²³]

(20) $$\eta =\frac{2}{\pi }\frac{1}{1+\frac{x_A}{W}}$$

The avalanche width (x_A) can be derived from the equation (17) as

(21) $$x_A=\frac{\mathit{[}\frac{E_{max}}{2}-\delta \mathit{(}A-B\mathit{)}\mathit{]}}{{\delta }^2\mathit{(}A+B\mathit{)}}$$

where $E_{max}=\delta \mathit{(}B-A\mathit{)}$

The depletion width on the other hand can also be derived from the equation (17) by setting the electric field as zero

(22) $$W=\frac{ln\mathit{(}B\text{/}A\mathit{)}}{2\delta }$$

IV. RESULTS AND DISCUSSION

In this section, variations of electric field with the length along the drift region for different parameters, efficiency variations with carrier concentration, oxide permittivity and oxide thickness have been studied. Besides efficiency comparison has been made for the junctionless SDR IMPATT and conventional SDR IMPATT. Fig. 3 depicts the variation of the electric field with length along the drift region for two different biasing voltages of 0.5 V and 0.35 V (equivalent electric fields of more than 10 *10 ⁷ V/m), applied across the device i. e. between P+ and N+ regions. For an applied bias of 0.5 V and 0.35 V, the electric field is maximum at the P+-N junction as expected where avalanche breakdown occurs. It is to be noted that in silicon avalanche breakdown occurs at a field of ~5 * 10 ⁷ V/m- for carrier concentration of 10²³/m³ which we have used in our calculations[²⁴]. It is thus established the occurrence of impact ionization at a biasing voltages of 0.5V and 0.35 V. The electric field decreases as we proceed along the drift region. Eventually it decreases to a value close to zero near the n+ region. Another significant observation is that the electric field decreases comparatively faster as the voltage, applied across the device is increased as with the increase of reverse bias, more and more electrons immobile acceptors are created in the N+ region and therefore the electric field decreases more rapidly at a higher reverse bias. It is depicted in Fig.4 that the electric field profile of the junctionless SDR IMPATT almost resembles that of a normal P+-N-N+ SDR IMPATT diode. In case of junctionless SDR, there may be some excess minority carrier concentration present in the very small gap (if present) between the region under P-gate and C-gate and also in the n-region due to imperfect conversion of the regions due to different metal work functions. So, the electric field decreases slightly in case of junctionless SDR compared to that of conventional SDR.

Fig.3
Electric field profile along the drift length L=20nm for two different applied voltages (V_r=0.5V, 0.35 V).

Fig.4
Electric field profile along drift length L=20nm for a junctionless SDR IMPATT and a conventional SDR IMPATT.

Fig. 5 represents the variation of the electric field with length along the drift region for two different n-region doping concentration Again as earlier the electric field is maximum at the p+-n junction as expected where avalanche breakdown occurs and it decreases as we proceed along the drift region and eventually it decreases to a value close to zero at the end of the depletion width which is near the N+ region. But here it is observed that the electric field decreases to zero comparatively earlier with the increase of substrate doping concentration of the n-region as the small electric field between the n-N+ regions vanishes with the increase of doping concentration (n-region is tending to a N+ region). Thus effectively, the extension of the depletion width in the n-region will be reduced thereby lowering the electric field near the N+ region.

Fig.5
Electric field profile along drift length L=20nm for two different carrier concentrations (N_db=10²⁰/m³, 10²³/m³).

Fig. 6 represents the variation of the efficiency of this device with the oxide permittivity. The efficiency of the device increases rapidly with the increase of oxide permittivity. With the decrease of oxide thickness, the capacitance between the n-region and C-gate increases and so the immobile carrier concentration decreases in the n-region. Thus, the depletion width will increase in the n-region, thereby increasing the efficiency. By using high K dielectrics the efficiency of this device can be increased. Moreover high K-dielectric also provides high immunity to the leakage current when the device is in off-state.

Fig.6
Variation of efficiency of junctionless SDR IMPATT device with the oxide permittivity for two different oxide thickness (t_ox= 5, 10 nm).

Fig. 7 depicts the variation of the efficiency of this device with the oxide thickness. The efficiency of the device increases with the reduction of the gate oxide thickness. Besides the efficiency of the device increases for smaller silicon substrate thickness. Higher efficiency can be achieved for silicon substrate thickness of 12nm compared to that of 15nm silicon substrate thickness as shown in the figure. It should be noted that with the decrease of oxide or silicon thickness, there is modulation of the immobile carrier concentration (decreases due to changeover of the N+ region to n-region) in the n-region and so the depletion width will increase as stated earlier and so the efficiency of the device will also increase.

Fig.7
Variation of efficiency of proposed junctionless SDR IMPATT device with the oxide thickness for two different silicon body thickness (t_si=12, 15 nm).

Fig. 8 represents the variation of the efficiency of this device with the oxide thickness as shown earlier in the Fig. 7 but here the variations have been shown for two different applied voltages 0.5 V and 0.35V. As it can be clearly observed that higher efficiency can be achieved for 0.35V compared to the applied voltage of 0.5V.

Fig.8
Variation of efficiency of junctionless SDR IMPATT device with oxide thickness for two different applied voltages (Vr=0.5V, 0.35V).

Fig. 9 shows the variation of the efficiency of a junctionless SDR IMPATT and a normal SDR IMPATT with the substrate carrier concentration. It can be observed that the efficiency of the proposed device is comparatively higher for the junctionless SDR IMPATT than that of a normal SDR IMPATT thereby making this junctionless device more attractive. It should be noted that the maximum electric field is less in case of junctionless SDR IMPATT due to the reasons already mentioned earlier and so the avalanche width being dependent on maximum electric field will be less (equation 21) thereby making the efficiency of a junctionless SDR IMPATT greater than that of a conventional SDR IMPATT

Fig.9
Variation of efficiency with the carrier concentration for a junctionless SDR IMPATT and a normal SDR IMPATT.

V. CONCLUSION

In the present work, utilizing the concept and advantages of a junctionless field effect transistor (JLTFET), an attempt has been made to present a new device structure which will function as a SDR (Single Drift Region) P+-N-N+ IMPATT diode The analytical modeling of the electric field profile and the investigation of the efficiency of the proposed device structure have been performed based on the solution of the 2D- Poisson's equation. The proposed device structure does not require any physical metallurgical junctions and no impurity doping for creating the P+ and N+ regions. However, the voltage applied across the P+ and N+ regions can modulate the breakdown voltage and hence the efficiency can also be modulated. The electric field profile of our proposed structure resembles the electric field profile of a normal SDR IMPATT diode and without any physical doping greater efficiency can be achieved than that of a normal SDR IMPATT diode and also the efficiency can be increased by varying oxide permittivity, oxide thickness and applied voltage. However we feel it will be better if we decide the practical implementations only after fabrication and detailed characterization of these devices.

REFERENCES

• ^[1]
  Sitesh kumar roy, Monojit Mitra, “Microwave Semiconductor Devices,” Prentice-Hall of India Private Limited, New Delhi 2003.
• ^[2]
  G. Venkateshwar Reddy and M. Jagadesh Kumar, “A New Dual-Material Double-Gate (DMDG) Nanoscale SOI MOSFET—Two-Dimensional Analytical Modeling and Simulation, “ IEEE Trans. NanoTechnology, S, vol. 4, no. 2, pp. 260-268, March 2005.
• ^[3]
  Bibhas Manna, Saheli Sarkhel, Nurul Islam, S. Sarkar, and Subir Kumar Sarkar, “Spatial Composition Grading of Binary Metal AlloyGate Electrode for Short-Channel SOI/SON MOSFET Application”, IEEE Trans. Electron Devices, S, vol. 59, no. 12, pp. 3280-3287, December 2012.
• ^[4]
  Sourav Naskar and Subir Kumar Sarkar, “Quantum Analytical Model for Inversion Charge and Threshold Voltage of Short-Channel Dual-Material Double-Gate SON MOSFET, “IEEE Trans. Electron Devices, S, vol. 60, no. 9, pp. 2734– 2740, September 2013.
• ^[5]
  Sharmistha Shee, Gargee Bhattacharyya, and Subir Kumar Sarkar, “Quantum Analytical Modeling for Device Parameters and I -V Characteristics of Nanoscale Dual-Material Double-GateSilicon-on-Nothing MOSFET, “ IEEE Trans. Electron Devices, S, vol. 61, no. 8, pp. 2697-2704, August 2014.
• ^[6]
  Xiaoshi Jin, Xi Liu, Hyuck-In Kwon, Jung-Hee Lee, Jong-Ho Lee, “A subthreshold current model for nanoscale short channel junctionless MOSFETs,” Solid-State Electronics vol. 82, pp. 77-81,Oct 2013.
• ^[7]
  Lee CW, Afzalian A, Akhavan ND, Yan R, Ferain I, Colinge JP., “Junction-less multigate field-effect transistor”, J. Appl. Phys., vol. 94(5), pp. 053511-053511-2, Feb. 2009.
• ^[8]
  Lee CW, Borne A, Ferain I, Afzalian A, Yan R, Akhavan ND, “Hightemperature performance of silicon junctionless MOSFETs”, IEEE Trans. Electron Devices, S, vol. 57, no. 3, pp. 620-5, March 2010.
• ^[9]
  Park CH, Ko MD, Kim KH, Baek RH, Sohn CW, Baek CK, “Electricalcharacteristics of 20-nm junctionless Si nanowire transistors, “Solid-State Electron, vol. 73, pp. 7-10, July 2012.
• ^[10]
  Ansari L, Feldman B, Fagas G, Colinge JP, Greer JC., “Subthreshold behavior of junctionless silicon nanowire transistors from atomic scale simulations,” Solid-State Electron., vol. 71, no. 11, pp. 58-62, May 2012.
• ^[11]
  Colinge JP, Lee CW, Afzalian A, Akhavan ND, Yan R, Ferain I, “Nanowire transistors without junctions,” Nature Nanotech., vol. 5, pp. 225-9, Feb 2010.
• ^[12]
  Dalle C, Rolland P, Lieti G, “Flat doping profile double-drift silicon IMPATT for reliable CW high power high-efficiency generation in the 94-GHz window,” IEEE Trans. Electron Devices, S, vol. 37, no. 1, pp. 227-236, Jan 1990.
• ^[13]
  Luy JF, Casel A, Behr W, Kasper E, “A 90-GHz double-drift IMPATT diode made with Si MBE,” IEEE Trans. Electron Devices, S, vol. 34, no. 5, pp. 1084-1089, May 1987.
• ^[14]
  Luschas M, Judaschke R, Luy JF (2002b), “Simulation and measurement results of 150 GHz integrated silicon IMPATT diodes”, in IEEE MTT-S International Microwave Symposium Digest June 2002, vol. 2, pp 1269-1272.
• ^[15]
  Tapas Kumar Pall and J. P. Banerjee2, “Study of Efficiency of Ka-band IMPATT Diodes and Oscillators around Optimized condition,” International Journalof Advanced Science and Technology, vol. 26, Jan 2011.
• ^[16]
  D. Ghosh, B. Chakrabarti, M. Mitra “A Detailed Computer Analysis of SiC And GaN Based IMPATT Diodes Operating at Ka, V And WBand”, International Journal of Scientific & Engineering Research, vol. 3(2), Feb 2012 1, ISSN 2229-5518.
• ^[17]
  L. P. Mishra, S. Chakraborty, M. Mitra, “A Computer Method for studying unction Depth of SDR IMPATTdiode and a Comparisonofits Performance Based different SemiconductorMaterials”, International Journal of Engineering Science and Technology (IJEST), vol. 3, no. 6, June 2011, ISSN: 0975-5462.
• ^[18]
  Yogesh Goswami, Bahnimann Ghosh and Pranav Kumar Asthana, “Analog performance of Si junctionless tunnel field effect transistor and its improvisation using III-v semiconductor,” RSC Adv., vol. 4, pp. 10761-10765, Jan 2014, DOI: 10.1039/c3ra46535g.
  » https://doi.org/10.1039/c3ra46535g
• ^[19]
  M. W. Akram, Bahniman Ghosh, Punyasloka Bal, Partha Mondalm, ’T-type double gate junctionless tunnel field effect transistorm,” Journal of Semiconductors, vol. 35, no.1, Jan 2014.
• ^[20]
  SM. Sze “Physics of Semiconductor Devices,” John Wiley & Sons, Inc., Hoboken, New Jersey 2005.
• ^[21]
  K. Konrad Young, ”Short-Channel Effect in Fully Depleted SO1MOSFET's,” IEEE Trans. Electron Devices, vol. 36, no. 2, pp. 399-402, Feb 1989.
• ^[22]
  F. Jazaeri, L. Barbut, A. Koukab, J. -M. Sallese, “Analytical model for ultra-thin body junctionless symmetric double gate MOSFETs in subthreshold regime, “Solid-State Electronics, vol. 82, pp. 103-110, Apr. 2013.
• ^[23]
  MS. Tyagi, “Introduction to Semiconductor materials and Devices,” John Wiley & Sons, Inc., Hoboken, New Jersey 1991, pp. 312-317.
• ^[24]
  B. J. Baliga, “Fundamentals of Power Semiconductor Devices,” Springer Science 2008, pp. 91-100, DOI: 10. 1007/978-0-387-47314-7_3.
  » https://doi.org/10.1007/978-0-387-47314-7_3

Publication Dates

• Publication in this collection
  June 2017

History

• Received
  30 June 2016
• Reviewed
  30 June 2016
• Accepted
  17 Feb 2017