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Pentacene based thin film transistors with high-k dielectric Nd2O3 as a gate insulator


We have investigated the pentacene based Organic Thin Film Transistors (OTFTs) with High-k Dielectric Nd2O3. Use of high dielectric constant (high-k) gate insulator Nd2O3 reduces the threshold voltage and sub threshold swing of the OTFTs. The calculated threshold voltage -2.2V and sub-threshold swing 1V/decade, current ON-OFF ratio is 1.7 × 10(4) and mobility is 0.13cm²/V.s. Pentacene film is deposited on Nd2O3 surface using two step deposition method. Deposited pentacene film is found poly crystalline in nature.

Pentacene; Organic Thin Film Transistors; Low Threshold voltage; Rare earth oxide Nd2O3; Two Step Deposition

Pentacene based thin film transistors with high-k dielectric Nd2O3 as a gate insulator

R. SarmaI; D. SaikiaI, II; Puja SaikiaII, * * Electronic address: ; P.K.SaikiaII; B.BaishyaII

IThin Film Laboratory, Department of Physics, J B College, Jorhat, Assam, India

IIDibrugarh University, Dibrugarh, Assam, India


We have investigated the pentacene based Organic Thin Film Transistors (OTFTs) with High-k Dielectric Nd2O3. Use of high dielectric constant (high-k) gate insulator Nd2O3 reduces the threshold voltage and sub threshold swing of the OTFTs. The calculated threshold voltage -2.2V and sub-threshold swing 1V/decade, current ON-OFF ratio is 1.7 × 104 and mobility is 0.13cm2/V.s. Pentacene film is deposited on Nd2O3 surface using two step deposition method. Deposited pentacene film is found poly crystalline in nature.

Keywords: Pentacene, Organic Thin Film Transistors, Low Threshold voltage, Rare earth oxide Nd2O3, Two Step Deposition.


Organic Thin Film Transistors(OTFTs) have received considerable attention from the standpoint of developing low-cost or large-area electronics applications like electronic paper displays, flexible sensors, and disposable radio frequency identification tags [1]. In recent years, many studies have been devoted to improving the characteristics of organic thin-film transistors (OTFTs) [2]. Pentacene organic semiconductors have become one of the most promising materials for future thin, light, and flexible display applications. However, there are many problems still unresolved such as low mobility, high driving voltages, etc. There have been many investigations for improving mobility and other performances of OTFTs. The performance of the OTFTS can be improved by proper selection of Gate dielectric material and metal electrodes (metals which can give good ohmic contact) [3]. Most successful gate dielectric for pentacene based OTFTs is thermally grown silicon dioxide but the operating voltage of these silicon dioxide insulated OTFTs is large, above 20 V. For portable applications, especially for radio frequency identification devices requiring low power consumption, it is necessary to reduce the operating voltage to below 5 V. The key to low voltage operation is reduction of threshold voltage and sub threshold swing. The use of a high dielectric-constant (k) gate dielectric lowering the operation voltage of TFTs is one of the main technical trends [4,5]. Therefore researchers all over the world worked on the way to reduce operating voltage of pentacene based OTFTs using various high dielectric constant insulators Al2O3 [4], HfLaO [5,6], HfSiOx [7], Pr6O11 [8], La2O3 [9] etc. However, though the dielectric capacitance and strength of the gate dielectric are incredibly important properties, the surface characteristics of the gate dielectric can also play a vital role. High dielectric-constant (k) gate dielectric are characterized by a relatively rough surface morphology upon deposition in a vacuum chamber. The rough surfaces result in an inferior channel/dielectric interface along with poor crystalline growth of the pentacene channel, and thus OTFTs fabricated on such dielectric surfaces usually exhibit undesirable device characteristics with low current ON-OFF ratio. Very thin or high-k gate dielectrics generally may bring about high leakage current and low dielectric strength in the utilization of OTFTs.

The rare earth oxides (Nd2O3), Er2O3, Pr2O3,ZrO2 etc., are reported with very high dielectric constant and low leakage current reliable for gate dielectrics in microelectronics [10,11]. One of us Baishya [12] study the suitability of rare earth oxides in thin film transistors. One of the above neodymium oxide (Nd2O3) as high-k gate dielectric has been under intense investigation recently for replacing conventional SiO2 due to its high dielectric constant and low leakage current. The properties of grown film and interface show a pronounced dependence upon the deposition process and the precise deposition parameters. Many techniques such as chemical vapor deposition, atomic layer deposition, sol-gel techniques, electron beam deposition etc. are used to deposit thin films on the aforementioned rare earth oxides. Each technique has their own set of advantages and disadvantages. However, most of these techniques show some or other kind of interface damage [13]. Sputtering and e-beam assisted depositions create radiation induced surface damage during film growth. Thermal evaporation is a well known technique that does not produce any kind of surface damage [13,14]. Because this technique is a rather gentle process it creates very little or no damage to the interface [13].

Inorganic TFTs with thermally evaporated Nd2O3 oxide insulating layer reported successfully from this laboratory [15,16]. Structure and Electrical Properties of Thermally Evaporated Nd2O3 thin films was studied by Kannan et al. [17,18] and reported that the thermally deposited films thickness bellow 2650Å shows well amorphous structure. Amorphous dielectric films are usually insensitive to impurities and [7,19] and more stable owing to the absence of grain boundaries hence suitable for gate insulator.

Further in this work we use two-step-deposition technique [20,21] to improve the film quality of semiconductor layer over Nd2O3 dielectric surface. The two-step-deposition (TSD) technique, based on controlling deposition rate (DR) [22,23]. This technique enables us to control the channel conductivity in the depletion and accumulation regime as well as to improve the film continuity [20,21]. The substrate temperature is kept at 270C during deposition because it is found that [24] at that temperature best poly crystalline thin films of pentacene can be grown.

The performance of the OTFT also depends on the contact electrode [25]. We have [8,9,26] already studied pentacene and tetracene based OTFTs using Al contact electrode and it is found that that best result cannot be obtained with Al-source drain electrode. As a source/drain (S/D) electrode, currently, gold has been mainly used as a contact metal in pentacene based OTFTs because gold has a work function of 5.1 eV, which is close to the highest occupied molecular orbital(HOMO) level of pentacene (5.0 eV). As a result hole injection barrier is low so that carriers can move easily in each direction between electrode and pentacene. Therefore in this work we use Au as source drain contact electrode.


OTFTs were fabricated in staggered electrode structures by a series of vacuum evaporations using suitable masks. The order of the deposition is shown in Fig. 1. In the fabrication process first Al-gate electrodes of thickness 1010Å is deposited over ultrasonically cleaned (with acetone, ethanol and de-ionized water) glass substrate, above which a layer of Nd2O3 of thickness 650Å is deposited. The oxide was properly degassed in vacuum for a long time prior to deposition. Following the oxide layer a layer of pentacene (Aldrich of 99.9%purity), thickness 380Å is deposited using the two-step deposition method. First monolayer of 120Å was growth using 0.5 Å/s deposition rate and the next layer of thickness 260Å deposited with the rate 0.1 Å/s. Finally the source drain electrodes of Au (thickness 1430Å) are deposited using shadow mask having a channel of length 50µm and width 0.14 cm. All the depositions are done at room temperature (270C) and at a vacuum better than 5 × 10-6 torr using thermal evaporation method. The experimental arrangement to study the electrical properties of the OTFTs is shown in figure 2.


Drain current ID versus drain voltage VD at various VG are plotted in Figure 3, The graphs established that the OTFTs operate in the accumulation mode and Pentacene is p-type semiconductor. In saturation region VD = VG – VT; drain current is given by Eq. 1 [3] -

where w is the channel width, L is channel length, ci is the capacitance per unit area of the gate insulator, VT is the threshold voltage and µ is the mobility.

Plot of (IDsat)1/2 versus VG is shown in the Figure 4. The field effect mobility m is calculated from the slope of this plot. The threshold voltage VT is estimated by the extrapolation of the linear portion of the graph to the VG axis [3]. Plot of Log (ID) versus VG at a constant drain voltage(-15V) is shown in the Figure 5. The sub-threshold swing is calculated from the slope of this graph using the relation (2)[27] -

The current ON-OFF ratio is estimated from the relation (3)[3]

The J-V characteristics of the dielectric film in Al/Nd2O3/Au configuration is shown in the figure 6. The films shows very low leakage current and hence suitable for OTFTs. In Figure 7 the XRD pattern of the pentacene film deposited over Nd2O3 is shown. The observed diffraction peaks established that thin films of Pentacene grown over Nd2O3 by two step deposition method at 270C is poly crystalline in nature and consist of only thin film phase. The various parameters used and evaluated in this work are tabulated in table 1. In table 2 a comparative study with the previous works is done. From the comparative study it is clear that Nd2O3 will be better insulator for low voltage pentacene based OTFTs. Though the mobility of the OTFTs with SiO2 insulator is a little better, the threshold voltage is considerably less in our case.


Using two step deposition on Nd2O3 dielectric we fabricate low threshold voltage OTFTs. The threshold voltage and sub threshold swing of the OTFTs are low enough so that they can be used in portable devices. Numbers of works on low threshold voltage OTFTs have been reported but in those works complicated fabrication techniques some times more than one fabrication technique and insulating layers are used. In this work we use traditional fabrication technique which is widely applied in commercial fabrications of TFTs, now a days. The comparative study in the table 2 established the superiority of the present work over the others. Using this method fabrication of low cost OTFT will become possible so that the traditional Si-TFTs can be replaced.


The authors R. Sarma and D. Saikia are thankful to University Grant Commission, New Delhi, India for financial support under major research project program Grant No.: 34-20/2008 (SR). Special thanks to Google Research Help Group.

(Received on 19 June, 2010)

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  • Publication Dates

    • Publication in this collection
      27 Sept 2010
    • Date of issue
      Sept 2010


    • Received
      19 June 2010
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